High speed CMOS clock generator

Details High speed CMOS clock generator High speed CMOS clock generator

1984-08-29

1987-01-13

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307482, 307578, 307452, H03K 19096, H03K 1901, H03K 1704, H03K 458

Patent

active

046366571

ABSTRACT:
A -CMOS clock generator circuit is controlled by two clocks, one always going high before the other when entering an active cycle, and always going low before the other in entering a precharge cycle; this one clock precharges a capacitor through a P-channel transistor, and holds a drive node discharged. Two sets of semi-connected N-channel output transistors are used, with the gates of the top two driven by the drive node, and the gates of the bottom two driven by a CMOS inverter which has the second clock as its input. The inverter output also drives the gate of a P-channel transistor between the capacitor and the drive node. Another P-channel transistor with the first clock on its gate couples the drive node to the intermediate node of the first output pair. The second clock transfers the charge from the capacitor to the drive node, which also causes the capacitor to boot the drive node above the supply. When the first clock goes low it discharges the booted node to the supply rather than to ground.

REFERENCES:
patent: 4508978 (1985-04-01), Reddy
patent: 4521701 (1985-06-01), Reddy
patent: 4542310 (1985-09-01), Ellis et al.

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