High speed CMOS bus driver circuit that provides minimum output

Details High speed CMOS bus driver circuit that provides minimum output High speed CMOS bus driver circuit that provides minimum output

1992-06-08

1994-06-14

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 3072968, 307473, H03K 19003, H03K 190948

Patent

active

053213190

ABSTRACT:
A high speed bus driver circuit is disclosed that minimizes output signal oscillation by maintaining the clamp voltage at specified levels. The driver circuit includes a pair of voltage preference circuits that are designed to deliver the appropriate clamp voltages even at the best case speed corners, the circuit prevents simultaneous turn on of drive transistors, equalizes the propagation delay and provides for first access for tristating the bus driver transistors.

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patent: 5029283 (1991-07-01), Ellsworth et al.
patent: 5109187 (1992-04-01), Guliani
patent: 5136182 (1992-08-01), Fawal
patent: 5182468 (1993-01-01), Erdelyi et al.

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