High-speed CMOS buffer with controlled slew rate

Details High-speed CMOS buffer with controlled slew rate High-speed CMOS buffer with controlled slew rate

1987-08-27

1991-01-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307270, 307585, H03K 19094, H03K 1716, H03K 301, H03K 17687

Patent

active

049873245

ABSTRACT:
A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control inverter having a switching threshold voltage higher than that of the first control inverter. The gate of the N channel transistor in the second inverter is controlled by a third control inverter having a switching threshold voltage lower than that of the first control inverter.

REFERENCES:
patent: 3631528 (1971-12-01), Green
patent: 4103188 (1978-07-01), Morton

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