High speed clocked, latched, and bootstrapped buffer

Details High speed clocked, latched, and bootstrapped buffer High speed clocked, latched, and bootstrapped buffer

1984-10-16

1986-10-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307453, 307481, 307482, 307578, 307269, 307279, 307601, 307605, H03K 19096, H03K 19017

Patent

active

046174761

ABSTRACT:
From an input signal, a buffer circuit derives an output signal which changes in logic state in synchronism with the rising edges of a first clock and whose value follows the input signal but in opposite logic state. The first clock directly drives the buffer output through a first transistor whose gate is controlled by the output of a NOR-gate. The buffer output is connected to ground through two FET's whose gates are controlled respectively by the first clock and the input signal as sampled by a second clock. The buffer output after being delayed and the input signal as sampled by the second clock are applied to the inputs of the NOR-gate. By adding an FET between the gate of the first transistor and the output of the NOR-gate the bootstrap action caused by the gate-drain parasitic capacitance of the first transistor reduces the delay between the rise of the buffer output and the rising edge of the first clock. A holding circuit may be used to hold the value of the buffer output despite changes in the states of the clocks.

REFERENCES:
patent: 3732442 (1973-05-01), Husbands et al.
patent: 4063117 (1977-12-01), Laugesen et al.
patent: 4381460 (1983-04-01), Menachem
patent: 4449066 (1984-05-01), Aoyama et al.
patent: 4463273 (1984-07-01), Dingwall
patent: 4472644 (1984-09-01), Kirsch
patent: 4490633 (1984-12-01), Nouter et al.
patent: 4542307 (1985-09-01), Baba
patent: 4549101 (1985-10-01), Sood
Mead and Conway, Introduction to VLSI Design, Addison-Wesley Pub. Co., Reading, Mass., Oct. 1980, p. 165.

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