High speed clock driving circuitry for interline transfer CCD im

Details High speed clock driving circuitry for interline transfer CCD im High speed clock driving circuitry for interline transfer CCD im

1991-08-14

1993-08-17

Razavi, Michael T.

Facsimile and static presentation processing

Facsimile

Recording apparatus

35821315, 358209, H04N 5335

Patent

active

052374220

ABSTRACT:
Clock driving circuitry for a high speed interline transfer CCD imager generates complementary voltage waveforms, each of which shifts from a respective first voltage level to a respective second voltage level once for every line in a frame to empty each of the imager's vertical shift registers in succession and to a respective third voltage level once each frame to charge all of the photodiodes of the imager. In generating one of the complementary waveforms, a positive third voltage level is superimposed upon the waveform through at least one isolation device and a separate switch is provided to discharge the waveform back to the second voltage level. In generating the other of the complementary waveforms, the waveform is switched from the second voltage level to a negative third voltage level and then switched back from the negative third voltage level to the second voltage level. Filtering is provided to remove transients generated by switching the latter wave from the negative third voltage level back to the second voltage level.

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