High speed clock distribution system

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307262, 328155, 328 62, 328 63, 328105, 328 55, H03K 513, H03K 500

Patent

active

050878298

ABSTRACT:
This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

REFERENCES:
patent: 4789996 (1988-12-01), Butcher
patent: 4847870 (1989-07-01), Butcher
Anceau, "A Synch. Approach for Clocking VLSI Systems", IEEE Journal of S.S.C., vol. SC-17), Feb. 82, pp. 51-56.
Blum, "Automatic Adjustment of Several Decentrally Generated Clock . . . ", IBM Tech. Dis. Bulletin, vol. 24, No. 2, 7/81.
Koetzle, "Computer Clock Distribution System w/Prog. Delay & Auto Adjust." IBM TBB, vol. 18, No. 6, 11/75.

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