Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-08-20
2003-03-04
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C326S083000
Reexamination Certificate
active
06529050
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock buffer and, more particularly, to a high-speed clock buffer that has a substantially reduced crowbar current.
2. Description of the Related Art
A clock buffer is a device that drives a clock signal onto a capacitive load such as, for example, a clock tree. Current generation clock trees, where a single clock signal drives a number of clock inputs, typically have a loading capacitance that ranges from approximately 10 pF to 100 pF, depending on the size of the system.
There are many applications, such as in communication networks, where the edge transitions of the clock signal are critical to the operation of the system. Thus, it is critical to those systems that the clock buffer has sufficient drive for the load which, in the case of a clock tree, can be substantial.
FIG. 1
shows a schematic diagram that illustrates a conventional clock buffer
100
. As shown in
FIG. 1
, buffer
100
includes an inverter
110
and a driver inverter
120
. Inverter
110
has an input and an output, while driver inverter
120
has an input that is connected to the output of inverter
110
, and an output.
As shown in
FIG. 1
, driver inverter
120
includes a p-channel transistor P
1
and an n-channel transistor N
1
. P-channel transistor P
1
has a source connected to VCC (a power supply node), a drain, and a gate connected to the output of inverter
110
. N-channel transistor N
1
has a source connected to ground, a drain connected to the drain of transistor P
1
, and a gate connected to the output of inverter
110
.
Transistors P
1
and N
1
are sized to provide sufficient drive to the load. As a result, transistors P
1
and N
1
are typically much larger than the transistors used to form inverter
110
. In addition, as the capacitive loading (of the clock trees) increases, it is common practice to further increase the sizes of transistors P
1
and N
1
to provide the extra current drive.
In operation, inverter
110
receives a clock signal CLK, inverts the clock signal CLK, and outputs a first inverted clock signal CLK
1
. Driver inverter
120
, in turn, receives the first inverted clock signal CLK
1
, inverts the clock signal CLK
1
, and outputs a second inverted clock signal CLK
2
. Buffer
100
is non-inverting because the input clock signal CLK and the second inverted clock signal CLK
2
have the same logic state.
With respect to driver inverter
120
, p-channel transistor P
1
turns on and conducts when the source-to-drain voltage VSD is greater than zero (e.g., VSD>0), and the gate-to-source voltage VGS is less than the threshold voltage VTP of the transistor (e.g., VGS<VTP). N-channel transistor NI turns on and conducts when the drain-to-source voltage VDS is greater than zero (e.g., VDS>0), and the gate-to-source voltage VGS is greater than the threshold voltage VTN of the transistor (e.g., VGS>VTN).
One of the advantages of buffer
100
is that when the voltages of the clock signal CLK and the first inverted clock signal CLK
1
are at CMOS levels, no current is dissipated. For example, when the voltage of the first inverted clock signal CLK
1
is at ground, p-channel transistor P
1
is turned on and n-channel transistor N
1
is turned off. Similarly, when the voltage of the first inverted clock signal CLK
1
is at VCC, p-channel transistor PI is turned off and n-channel transistor N
1
is turned on.
One of the disadvantages of buffer
100
, however, is that transistors P
1
and N
1
of inverter
120
both turn on and conduct during a portion of the rising and falling edges of the inverted clock signal CLK
1
. (The transistors of inverter
110
also turn on and conduct during a portion of the rising and falling edges of the clock signal CLK, but since the transistors that make up inverter
110
are substantially smaller than transistors P
1
and N
1
the effect is much less significant.)
Although clock signals are typically depicted as instantaneously changing logic states (from a logic low to a logic high or vice versa), in actual practice a finite time, such as 100-200 pS, is required for the signal to change logic states, particularly if a relatively large capacitive load is present.
FIG. 2
shows a timing diagram that illustrates the first inverted clock signal CLK
1
input to inverter
120
. As shown in
FIG. 2
, clock signal CLK
1
starts as a logic low voltage VL at time t
0
, and begins transitioning from a logic low to a logic high at time t
1
. At time t
2
, clock signal CLK passes a turn on voltage V
1
for transistor N
1
(equal to the threshold voltage VTN of transistor N
1
), and at time t
3
passes a turn off voltage V
2
for transistor P
1
(where the gate-to-source voltage is greater than the threshold voltage VTP). Clock signal CLK
1
then reaches a logic high voltage VH at time t
4
.
From time t
0
to time t
1
, transistor P
1
is turned on charging the load to a logic high, while transistor N
1
is turned off. At time t
2
, however, the voltage on the gates of transistors P
1
and N
1
has risen to a point where the gate-to-source voltage (VGS) of transistor N
1
is greater than the threshold voltage of transistor N
1
. As a result, transistor N
1
turns on.
Thus, both transistors P
1
and N
1
remain turned on until clock signal CLK
1
passes time t
3
when the gate-to-source voltage (VGS) of transistor P
1
is no longer less than the threshold voltage of transistor P
1
. This, in turn, causes transistor P
1
to turn off. Thus, from time t
2
to time t
3
(about 80% of the rise time), both transistors P
1
and N
1
are turned on. A similar situation occurs on the falling edge of clock signal CLK
1
.
When transistors P
1
and N
1
are both turned on at the same time, a current ICB (see FIG.
1
), known as a crowbar current, flows directly from transistor P
1
to transistor N
1
. The crowbar current is an undesirable current because the crowbar current consumes power and slows down the response time of the circuit by increasing the rise and fall time of the clock signal CLK
2
.
The rise and fall times are increased because the crowbar current ICB that is sunk by transistor N
1
is unavailable to charge the load on the falling edge of the clock signal CLK
1
, and limits the current that can be sunk from the load on the rising edge of the clock signal CLK
1
. By restricting the current that can be used to charge or discharge the load, the rise and fall times are necessarily increased. In addition, the crowbar current can cause supply and ground noise. Thus, there is a need for a driver inverter that substantially reduces the crowbar current.
SUMMARY OF THE INVENTION
The present invention substantially reduces the crowbar current in a driver inverter, which has a pair of complementary driver transistors, by adjusting the turn on and turn off times of the driver transistors such that each driver transistor turns on after the other driver transistor has turned off.
A buffer in accordance with the present invention includes a pull up block that receives an input signal which, in turn, has a plurality of edges. The pull up block outputs a first signal in response to the input signal a delay time after the input signal is received. The first signal beginning a transition from a first logic level to a second logic level at a first time.
The buffer also includes a first driver transistor that is connected to the pull up block and an output node. The first driver transistor receives the first signal, sources a first current to the output node when a voltage level of the first signal is in a first voltage range, and stops the first current when the voltage level of the first signal is in a second voltage range.
The buffer further includes a pull down block that is connected to the pull up block. The pull down block receives the input signal and outputs a second signal in response to the input signal a delay time after the input signal is received. The second signal beginning a transition from the first logic level to the second logic level at a second time. The second t
Hoang Tuong
Kuo James R.
National Semiconductor Corporation
Pickering Mark C.
Wells Kenneth B.
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