Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2003-01-30
2004-12-07
Vigushin, John B. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C361S780000, C361S794000
Reexamination Certificate
active
06828514
ABSTRACT:
TECHNICAL FIELD
This invention relates to multilayered printed circuit boards (PCBs) and to methods of making same. More particularly, the invention relates to such boards of the high speed type.
BACKGROUND OF THE INVENTION
As operational requirements increase for electronic structures such as electronic components, e.g., semiconductor chips and modules including same, which mount on PCBs and are coupled together through the board's circuitry, so too must the host PCB be able to compensate for same. One particular increase has been the need for higher frequency connections between the mounted components, which connections, as stated, occur through the underlying host PCB. Such connections are subjected to the detrimental effects, e.g., signal deterioration, caused by the inherent characteristics of such known PCB wiring. For example, signal deterioration is expressed in terms of either the “rise time” or the “fall time” of the signal's response to a step change. The deterioration of the signal can be quantified with the formula (Z
0
*C.)/2, where Z
0
is the transmission line characteristic impedance, and C is the amount of the via capacitance. In a wire having a typical 50 ohm transmission line impedance, a plated through hole via having a capacitance of 4 pico farad (pf) would represent a 100 pico-second (ps) rise-time (or fall time) degradation, as compared to a 12.5 ps degradation with a 0.5 pf buried via of the present invention, as discussed below. This difference is significant in systems operation at 800 MHz or faster, where there are associated signal transition rates of 200 ps or faster.
A typical high performance PCB has not been able to provide wiring densities beyond a certain point due to limitations imposed by the direct current (DC) resistance maximum in connections between components (especially chips). Similarly, high speed signals demand wider lines than normal PCB lines to minimize the “skin effect” losses in long lines. To produce a PCB with all wide lines would be impractical, primarily because of the resulting excessive thickness needed for the final board. Such increased thicknesses are obviously unacceptable from a design standpoint.
Various PCBs are described in the following patents:
4,902,610
C. Shipley
5,336,855
J. Kahlert et al
5,418,690
R. Conn et al
5,768,109
J. Gulick et al
5,891,869
S. Lociuro et al
5,894,517
J. Hutchison et al
6,023,211
J. Somei
6,075,423
G. Saunders
6,081,430
G. La Rue
6,146,202
S. Ramey et al
6,222,740
K. Bovensiepen et al
6,246,010
R. Zenner et al
6,431,914
T. Biliman
6,495,772
D. Anstrom et al
US2002/0125967
R. Garrett et al
JP4025155A2
O. Takashi
The teachings of these documents are incorporated herein by reference.
As understood from the following, a primary purpose of the present invention is to provide an improved multilayered PCB which provides for enhanced high speed connections between electronic components mounted on the board. By the term “high speed” as used herein is of course meant to mean high frequency.
It is believed that such a board and method of making same would represent a significant advancement in the PCB art.
OBJECTS AND SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to enhance the multilayered PCB art, by providing such a board capable of high speed signal passage to interconnect electronic components mounted on the board.
It is another object of the invention to provide a method of making such a PCB.
According to one aspect of the invention, there is provided a PCB comprising a first multilayered portion including at least one dielectric layer and at least one conductive plane wherein the conductive plane includes signal lines capable of having signals pass therealong at a first frequency, and a second multilayered portion bonded to the first multilayered portion and adapted for having a plurality of electronic components electrically coupled thereto, the second multilayered portion including at least one dielectric layer and at least one conductive plane wherein the conductive plane of the second multilayered portion includes signal lines capable of having signals pass therealong at a higher frequency than the first frequency to thereby provide a high speed connection between at least two of the electrical components.
According to another aspect of the invention, there is provided a method of making a multilayered PCB wherein the method comprises the steps of providing a first multilayered portion including at least one dielectric layer and at least one conductive plane wherein the conductive plane includes signal lines capable of having signals pass therealong at a first frequency, providing a second multilayered portion adapted for having a plurality of electronic components electrically coupled thereto, the second multilayered portion including at least one dielectric layer and at least one conductive plane wherein the conductive plane of the second multilayered portion includes signal lines capable of having signals pass therealong at a higher frequency than the first frequency to thereby provide a high speed connection between at least two of the electrical components, and bonding the first and second multilayered portions.
According to yet another aspect of the invention, there is provided an information handling system comprising a PCB including a first multilayered portion including at least one dielectric layer and at least one conductive plane wherein said conductive plane includes signal lines capable of having signals pass therealong at a first frequency, and a second multilayered portion bonded to said first multilayered portion and adapted for having a plurality of electronic components electrically coupled thereto, said second multilayered portion including at least one dielectric layer and at least one conductive signal plane wherein said conductive signal plane of said second multilayered portion includes signal lines capable of having signals pass therealong at a higher frequency than said first frequency to thereby provide a high speed connection between at least two of said electrical components.
REFERENCES:
patent: 4902610 (1990-02-01), Shipley
patent: 5336855 (1994-08-01), Kahlert et al.
patent: 5418690 (1995-05-01), Conn et al.
patent: 5768109 (1998-06-01), Gulick et al.
patent: 5891869 (1999-04-01), Lociuro et al.
patent: 5894517 (1999-04-01), Hutchison et al.
patent: 5912809 (1999-06-01), Steigerwald et al.
patent: 5990564 (1999-11-01), Degani et al.
patent: 6023211 (2000-02-01), Somei
patent: 6075423 (2000-06-01), Saunders
patent: 6081430 (2000-06-01), La Rue
patent: 6146202 (2000-11-01), Ramey et al.
patent: 6222740 (2001-04-01), Bovensiepen et al.
patent: 6246010 (2001-06-01), Zenner et al.
patent: 6281446 (2001-08-01), Sakamoto et al.
patent: 6431914 (2002-08-01), Billman
patent: 6495772 (2002-12-01), Anstrom et al.
patent: 2002/0079568 (2002-06-01), Degani et al.
patent: 2002/0125967 (2002-09-01), Garrett et al.
patent: 2003/0007339 (2003-01-01), Harris et al.
patent: 4025155 (1992-01-01), None
Chan Benson
Lauffer John M.
Lin How T.
Markovich Voya R.
Thomas David L.
Endicott Interconnect Technologies, Inc.
Fraley Lawrence R.
Hinman, Howard & Kattell LLC
Vigushin John B.
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