High speed charge-pump

Details High speed charge-pump High speed charge-pump

1999-09-15

2001-05-08

Kim, Jung Ho (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S069000

Reexamination Certificate

active

06229345

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a charge-pump circuit generally and, more particularly, to a circuit configured to generate pulses of current which are injected into a subsequent loop filter in a PLL system.
BACKGROUND OF THE INVENTION
Many conventional charge pumps circuits are push-pull style tri-stating charge pumps which have trouble operating at very high speeds. Push-pull style charge-pumps rely on precise matching between pull-up and pull-down currents. Furthermore, the PMOS transistors frequently used in pull-up stages are slow and thus limit the speed of operation. Previous charge-pump circuits also require extra circuitry to maintain an adequate common mode at the charge-pump outputs.
FIG. 1
illustrates one conventional charge-pump circuit
10
. The charge-pump circuit
10
requires a separate multiplexer
12
. The circuit
10
is limited to the use of the multiplexer
12
.
FIG. 2
illustrates a conventional charge-pump circuit that can be found in U.S. Pat. No. 5,825,640. The push-pull style of charge-pump circuit of
FIG. 2
relies on precise matching between pull-up and pull-down currents. The circuit is limited to the speed of PMOS transistor MP used in the pull-up stage. Furthermore the conventional charge-pump shown requires extra circuitry to maintain an adequate common mode at the charge-pump output.
FIG. 3
illustrates a conventional charge-pump circuit that can be found in U.S. Pat. No. 5,734,279. The circuit of
FIG. 3
, similar to the circuit of
FIG. 2
, is limited to the speed of PMOS transistors M
1
and M
2
used in the pull-up stage. Furthermore, the conventional charge-pump shown requires extra circuitry to maintain an adequate common mode at the charge-pump output.
FIG. 4
illustrates a conventional charge-pump circuit that can be found in U.S. Pat. No. 5,734,279. The circuit of
FIG. 4
, similar to the circuits of FIG.
2
and
FIG. 3
, is limited to the speed of PMOS transistors M
9
-M
10
used in the pull-up stage. Furthermore the conventional charge-pump shown requires extra circuitry to maintain an adequate common mode at the charge-pump output.
FIG. 5
illustrates a conventional charge-pump circuit that can be found in U.S. Pat. No. 5,239,455.
FIG. 6
illustrates a conventional charge-pump circuit that can be found in U.S. Pat. No. 5,663,686. The circuit of
FIG. 6
requires extra circuitry to maintain an adequate common mode at the charge-pump output and precise matching between pull-up and pull-down currents. It also is very sensitive to the matching of CMOS transmission gate impedances.
FIG. 7
illustrates a conventional charge-pump circuit that can be found in U.S. Pat. No. 5,625,306. The circuit of
FIG. 7
, similar to the circuit of
FIG. 6
, requires extra circuitry to maintain an adequate common mode at the charge-pump output and precise matching between pull-up and pull-down currents.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a first input signal. The second circuit may be configured to generate a second current in response to a second input signal. The third circuit may be configured to present a first pulse of current at a first output or a second pulse of current at a second output in response to the first and second currents.
The objects, features and advantages of the present invention include implementing a charge-pump that may generate pulses of current that may (i) provide a higher operational speed, (ii) have more linear transfer function, (iii) provide matching pull-up and pull-down currents, (iv) implement an integrated multiplexer, (v) eliminate and/or reduce the need for common mode circuitry, (vi) have smaller input swings, and/or (vii) provide faster multiplexing operation.


REFERENCES:
patent: 5164685 (1992-11-01), Niemio
patent: 5239455 (1993-08-01), Fobbester et al.
patent: 5332930 (1994-07-01), Volk
patent: 5343167 (1994-08-01), Masumoto et al.
patent: 5625306 (1997-04-01), Tada
patent: 5663686 (1997-09-01), Tada
patent: 5699016 (1997-12-01), Federspiel et al.
patent: 5734279 (1998-03-01), Bereza
patent: 5801578 (1998-09-01), Bereza
patent: 5825640 (1998-10-01), Quigley et al.
patent: 6084479 (2000-07-01), Duffy et al.

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