Television – Receiver circuitry – Tuning
Reexamination Certificate
1996-09-23
2002-02-05
Lee, Michael (Department: 2714)
Television
Receiver circuitry
Tuning
C348S732000, C455S245100, C455S185100, C455S234100
Reexamination Certificate
active
06344882
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique and apparatus for use in broadcast signal receivers, such as, for example, TV sets, that automatically searches and stores channels in which broadcast signals exist. Additionally, the technique and apparatus provide very high speed broadcast signal discrimination for use during channel selection and switching operations.
2. Description of the Conventional Art
FIG. 1
is a block diagram of an automatic channel storage apparatus of a conventional TV set. Referring to
FIG. 1
, the conventional automatic channel storage apparatus comprises a tuner
1
, which selects the pertinent channel in accordance with the tuning data outputted from a microcomputer
8
. Tuner
1
outputs intermediate frequency signals to an intermediate frequency processing unit
2
, which processes the intermediate frequency signals of an image signal outputted from tuner
1
. Intermediate frequency processing unit
2
also detects the original image signal. An image/color/deflection processing unit
3
receives the image signal outputted from intermediate frequency processing unit
2
and converts it into a form adequate for display on a CPT
4
. A synchronization detection unit
5
is used to detect synchronous signals outputted from intermediate frequency processing unit
2
. Microcomputer
8
outputs, sequentially, a series of tuning data to tuner
1
.
In the conventional system, the automatic channel storage mode operates in the following manner. First, the key signals are inputted into a key matrix
6
to initialize an automatic channel storage mode operation. The storage mode operates to discriminate that a broadcast signal exists at the pertinent channel. Each time a synchronous signal is inputted through synchronization detection unit
5
, the associated tuned data is stored, as a channel, in memory
7
.
FIG. 2
is a detailed block diagram of tuner
1
and intermediate frequency signal processing unit
2
.
FIG. 2
represents a block diagram of tuner
1
and intermediate frequency signal processing unit
2
. Tuner
1
comprise a high frequency amplifier
1
a
to amplify the input high frequency signals obtained from the antenna
9
input based on the pertinent channel data inputted from microcomputer
8
to a phase locked loop (PLL) unit
1
b
. PLL unit
1
b
does PLL processing, also. PLL unit
1
b
adjusts the oscillation frequency of a local oscillation unit
1
c
. A mixing unit
1
d
receives the output of high frequency amplifier
1
a
and outputs any received signals at the frequency tuned, or set, by the frequency of local oscillation unit
1
c
. The output of mixing unit
1
d
is transmitted to a surface elastic wave filter
1
e
to shape the intermediate frequency of the output.
The output surface elastic wave filter
1
e
of tuner
1
is received by intermediate frequency signal processing unit
2
. Intermediate frequency signal processing unit
2
comprises an IF amplifier
2
a
to amplify the output of surface elastic wave filter
1
e
at a 1st, 2nd, and 3rd amplifiers. The amplified signal is sent to an image detector
2
b
to detect image signals and transmit the signals to an image amplifier
2
c
to amplify and output the image signals to image/color/deflection processing unit
3
and synchronization detection unit
5
. The output of image detector
2
b
is also sent to an AGC detector
2
d
to detect the AGC signals from the output of image detector
2
b
. The output of AGC detector
2
d
is amplified by an IF AGC amplifier
2
e
which output is, in turn, inverted and amplified by an RF AGC inversion amplifier
2
f.
Tuner
1
also contains a high frequency AGC amplifier
1
f
which amplifies the RF AGC voltage outputted from RF AGC inversion amplifier
2
f
. The RF AGC voltage has had the ripple removed by Resistor R
1
and Condenser C
1
. The RF AGC voltage ripple is removed after it is outputted from RF AGC inversion amplifier
2
f
. The output of high frequency AGC amplifier
1
f
is transmitter to high frequency amplifier
1
a
. Finally, the output of image detector
2
b
is outputted to the AFT voltage through the buffer
2
g.
FIGS.
3
(
a
) to
3
(
c
) are waveform diagrams of each unit of microcomputer
8
as shown in FIG.
1
.
FIG. 4
is a locus diagram of the automatic gain control voltage showing the tuning operation by conventional techniques. FIG.
5
(
a
) is a flow chart showing how the automatic channel storage mode is applied to conventional TV sets. Finally, FIG.
5
(
b
) is a flow chart showing a channel switching method of conventional TV sets.
The automatic channel storage mode and channel selection switching method of a conventional TV set is hereinafter described with reference to
FIGS. 1
,
5
a
, and
5
b
. When a televiewer outputs a pertinent key on the key matrix to carry out the automatic channel storage, microcomputer
8
perceives it, searches for the channels in which broadcast signals exist by increasing one by one the channel number, and stores those channel number perceived to have a broadcast signal in memory
7
. In case where the televiewer desires to switch the channel in operation he outputs the channel increase and decrease key (not shown) and the next channel selected, each time by up/down, is the next pertinent channel stored in memory
7
, during the automatic channel storage mode (described above), from the channel in use at present.
First, the automatic channel storage mode as shown in FIG.
5
(
a
) is described by reference to FIG.
1
and FIG.
4
. When the automatic channel storage mode is set up, microcomputer
8
first initializes the channels for tuning, step S
1
of
FIG. 5A
, and after operating the PLL data of the pertinent channel, outputs the operated PLL data to tuner
1
.
Accordingly, the first channel is selected at tuner
1
, and, at that time, microcomputer
8
stands by, for the time necessary, for reading the synchronous signals, that is, for the standby time (approximately 300 ms) which is the time it for the synchronous signals to be detected through surface elastic wave filter
1
e
of tuner
1
, image detector
2
b
of intermediate signal processing unit
2
, and synchronization detection unit
5
, step S
4
of
FIG. 5
a
. This is shown in the waveform diagrams of each unit of microcomputer
8
in FIG.
3
(
a
) and
3
(
b
). That is, if a channel switching signal, CD as shown in
3
(
a
), is outputted to the tuner (if a tuning data PLL DATA of the pertinent channel is outputted to the tuner), and if there is any broadcast signal, it takes approximately 300 ms until the recognition signal ID is inputted through synchronization detection unit
5
, as shown in the waveform diagram in FIG.
3
(
b
).
After confirming whether the synchronous signals exist in the channel selected at present through path, step S
5
of FIG.
5
(
a
), if any, it is discriminated that there exist a broadcast signal in the selected channel. The data of the pertinent channel (channel number or frequency) is stored in memory
7
.
In the following step, it is confirmed whether all channels have been searched, step S
7
in
FIG. 5
a
. If any channels remain to be searched, the channel number is increased by one (N+1, channel increase), step
5
B of
FIG. 5A
, and the search is repeated until all channels have been searched. After searching all channels, the operation is ended.
Secondly, the channel selection and switching method as shown in FIG.
5
(
b
) is described by reference to FIG.
1
and FIG.
4
. When a televiewer desires to switch a channel in operation he presses the numeric key corresponding to the pertinent channel number or selects the next channel using the channel increase and decrease keys. Microcomputer
8
operates the PLL DATA of the selected channel, and outputs it to tuner
1
, step S
1
of FIG.
5
B. Accordingly, the pertinent channel is selected at tuner
1
, and at that time microcomputer
8
stands by for the time necessary for reading exactly the synchronous signals, that is, the standby time is 300 ms until the synch
Kim Jea-Seong
Shim Bong-Chun
Lee Michael
LG Electronics Inc.
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