High speed cascode circuit with low power consumption

Details High speed cascode circuit with low power consumption High speed cascode circuit with low power consumption

2007-11-20

2009-12-29

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200

Reexamination Certificate

active

07639543

ABSTRACT:
A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed. The memory device comprising: a first current detecting circuit comprising a first transistor of a first conductive type coupled in a diode configuration, wherein current flows according to a reference cell through the first transistor; a second current detecting circuit comprising a second transistor of the first conductive type coupled in a diode configuration, wherein current flows according to a selected memory cell through the second transistor; a bias circuit comprising a third transistor of the first conductive type that is coupled to the first transistor by a current mirror configuration; and a differential amplifying circuit comprising a fourth transistor of the first conductive type which is coupled to the second transistor, wherein the differential amplifying circuit outputs a signal corresponding to a difference between current flowing through the third transistor and current flowing through the fourth transistor; and wherein the first transistor, the second transistor, the third transistor and the fourth transistor are comprised of one predetermined sized unit transistor element of the first conductive type, or are comprised of parallel couplings of predetermined sized unit transistor elements of the first conductive type.

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patent: 7542348 (2009-06-01), Kim
patent: 01-098195 (1989-04-01), None

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