High speed bus transceiver with fault tolerant design for hot pl

Details High speed bus transceiver with fault tolerant design for hot pl High speed bus transceiver with fault tolerant design for hot pl

1991-10-28

1993-06-15

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 370 851, H03K 19003

Patent

active

052202119

ABSTRACT:
A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.

REFERENCES:
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4595923 (1986-06-01), McFarland, Jr.
patent: 4736124 (1988-04-01), McFarland, Jr.
patent: 4825402 (1989-04-01), Jalali
patent: 4885484 (1989-12-01), Gray
patent: 4890010 (1989-12-01), Neudeck et al.
patent: 5043938 (1991-08-01), Ebersole

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