High speed burst read address generation with high speed transfe

Static information storage and retrieval – Magnetic bubbles – Guide structure

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395425, 36518902, 36518905, 36523003, 36523004, G11C 11408, G11C 11409, G06F 1200

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active

053455738

ABSTRACT:
A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse two high order addressed word responses with two low order addressed word responses of specific address sequences. These operations are utilized in all of the required address sequences within different subgroups.

REFERENCES:
patent: 4366539 (1982-12-01), Johnson et al.
patent: 4370712 (1983-01-01), Johnson et al.
patent: 5134699 (1992-07-01), Aria et al.
patent: 5191657 (1993-03-01), Ludwig et al.
patent: 5218686 (1993-06-01), Thayer
"Multiple and Burst Cycle Bus Transfers", i486.TM.Microprocessor, Nov. 1989, pp. 96, 98, 104-105.

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