High-speed buffer arrangement with no delay distortion

Details High-speed buffer arrangement with no delay distortion High-speed buffer arrangement with no delay distortion

1983-06-02

1986-03-11

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307601, 307602, 307603, H03K 19003, H03K 19092, H03K 501

Patent

active

045756465

ABSTRACT:
A buffer arrangement on an integrated circuit is disclosed which translates the voltage levels of logic signals without distortion. Generally, signal distortion results from the difference between the low-to-high propagation delay and the high-to-low propagation delay through an individual buffer. The arrangement includes two buffers (33, 36) having unknown distorting characteristics, arranged in series-inverting pairs (31, 33; 35, 36). The first buffer (33) generates a predistorted signal from the signal to be translated, which has a delay at each transition due to either the high-to-low or low-to-high propagation delay of that buffer. By inverting (35) and redistorting the predistorted signal through a second buffer (36), each transition in the signal at the output thereof is further delayed due to a propagation delay opposite in type to that which that same transition was delayed by the first buffer. Each transition in the output signal has a total delay equal to the sum of the high-to-low propagation delay of one buffer plus the low-to-high propagation delay of the other buffer. When both buffers are of the same type on the same integrated circuit, their distortion characteristics are equivalent; and each transition in the output signal is uniformly delayed so that the output signal is faithful in shape to the input signal.

REFERENCES:
patent: 3909633 (1975-09-01), Hall
patent: 3925689 (1975-12-01), Rubenstein
patent: 4247921 (1981-01-01), Itoh et al.
patent: 4305009 (1981-12-01), Miyagawa et al.
patent: 4314166 (1982-02-01), Bismarck
patent: 4412335 (1983-10-01), Froment et al.

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