Boots – shoes – and leggings
Patent
1983-02-14
1985-04-09
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 100
Patent
active
045105812
ABSTRACT:
A high speed data buffer array allocation circuit is provided in association with a plurality of buffer memories for directing high speed data into the memories. The circuitry employs high speed MOS technology to implement high speed switching and data allocation. The data packet input, generally from an uninterruptible source, is directed and written into a first available buffer memory. The memory can thereafter be read by a host computer. Flags are set indicating the availability of the memory for reading. The data buffer allocation circuit has a plurality of selection circuits connected in an ordered linear array for effectively passing therethrough to the circuit associated with the first available buffer, a data ready input signal. In response to the data ready input signal, the selection circuit and associated gating circuit provide the necessary control to direct the data to the associated memory and to thereafter leave a flag indicating the availability of data. The selection circuit further latches a pass-through element of the circuit to a conductive state whereby the next data ready input signal is passed to a succeeding buffer along said array. When data is read by, for example, the host computer, the buffer selection circuit returns to an operating state wherein the data ready signal is isolated from succeeding selection circuits and the data available flag is removed.
REFERENCES:
patent: 3032746 (1962-05-01), Kautz
patent: 3344406 (1967-09-01), Vinal
patent: 3348209 (1967-10-01), Brooks
patent: 3439342 (1969-04-01), Barton
patent: 3601546 (1971-09-01), Lee
patent: 3621152 (1971-11-01), Billings
patent: 3742466 (1973-06-01), Hamm et al.
patent: 3812371 (1974-05-01), Chin
patent: 3818461 (1974-06-01), Ward et al.
patent: 3859641 (1975-01-01), Clemons et al.
patent: 3925689 (1975-12-01), Rubenstein
patent: 4054747 (1977-10-01), Pachynski, Jr.
patent: 4079456 (1978-03-01), Lunsford et al.
patent: 4092713 (1978-05-01), Scheuneman
patent: 4121261 (1978-03-01), Blossey
patent: 4131940 (1979-01-01), Moyer
patent: 4136399 (1979-01-01), Chan et al.
patent: 4144562 (1979-03-01), Cooper
patent: 4145751 (1979-03-01), Carlow et al.
patent: 4153944 (1979-05-01), Grandle
patent: 4158235 (1979-06-01), Call et al.
patent: 4161778 (1979-07-01), Getson, Jr. et al.
patent: 4162520 (1979-07-01), Cook et al.
patent: 4169289 (1979-09-01), Shively
patent: 4185190 (1980-01-01), Bottard et al.
patent: 4195343 (1980-03-01), Joyce
patent: 4202042 (1980-05-01), Connors et al.
patent: 4225922 (1980-09-01), Porter
patent: 4229804 (1980-09-01), Imazeki
patent: 4229815 (1980-09-01), Cummiskey
patent: 4236225 (1980-11-01), Jansen et al.
patent: 4254464 (1981-03-01), Byrne
patent: 4258418 (1981-03-01), Heath
patent: 4261035 (1981-04-01), Raymond
patent: 4276609 (1981-06-01), Patel
patent: 4281393 (1981-07-01), Gitelman et al.
patent: 4281398 (1981-07-01), McKenny et al.
patent: 4291370 (1981-09-01), Charles
patent: 4297595 (1981-10-01), Huellwegen
patent: 4307461 (1974-06-01), Brickman et al.
patent: 4315312 (1982-02-01), Schmidt
patent: 4328580 (1982-05-01), Stockham, Jr. et al.
patent: 4330720 (1982-05-01), Moore
Prime Computer Inc.
Zache Raulfe B.
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