High-speed bit synchronizer with multi-stage control structure

Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator

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331 17, 331 23, 331 25, 331DIG2, 327156, 360 51, 375375, H03L 7087, H03L 7107

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055259359

ABSTRACT:
A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass filter (integrator) for outputting a voltage of a low frequency component to the VCO in response to an output of the phase difference output controller and an output of the frequency comparator gain limiter, and a frequency-divider for frequency-dividing the clock pulse from the VCO at a desired ratio.

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"An ECL gate array with integrated PLL--based clock recovery and synthesis of high speed data and telecom applications", by David Rosky, Bruce H. Coy, Mare Friedmann, 182/SPIE vol. 1577 High-Speed Fiber Networks and Channels (1991), pp. 182-191.

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