High speed bit interleaved time division multiplexer for multino

Details High speed bit interleaved time division multiplexer for multino High speed bit interleaved time division multiplexer for multino

1986-08-01

1989-03-21

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 84, H04J 304

Patent

active

048150746

ABSTRACT:
A bit interleaved time division multiplexer for multinode system is provided and includes a high speed bus, a plurality of aggregate common blocks, a plurality of channel common blocks, and a system controller which selects the aggregate and channel common blocks and which is connected to the bus. Each aggregate common block includes an address recognizer, a recorder for obtaining information according to a first frame format from an aggregate line, supplying an intramultiplexer system address for at least one bit of the obtained information, and sending the information accompanied by the intramultplexer system address onto the high speed bus, and a recorder and transmitter for receiving bits of information from the high speed bus, multiplexing the information according to a second frame format and sending the so-multiplexed information out over an aggregate line. Each channel common block includes a channel address recognizer, a channel decoder for receiving information from the high speed bus and sending the information to its proper channel, and a channel multiplexer for multiplexing information from a plurality of channels into a bit stream according to a third frame format, sending the bit stream onto the high speed bus, and supplying an intramultiplexer system address to accompany the bits of the bit stream.

REFERENCES:
patent: 4375681 (1983-03-01), Abbott et al.
patent: 4488293 (1984-12-01), Haussmann et al.
patent: 4685101 (1987-08-01), Segal et al.

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