High-speed bipolar-field effect transistor (BI-FET) circuit

Details High-speed bipolar-field effect transistor (BI-FET) circuit High-speed bipolar-field effect transistor (BI-FET) circuit

1992-04-01

1994-02-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307443, 3072722, H03K 1908

Patent

active

052870162

ABSTRACT:
A process and hold system includes a bipolar logic section which is clocked on and off by a first field effect transistor and a bipolar latch section which is clocked on and off by a second field effect transistor. Emitter coupled logic is used in both the logic and latch sections in order to obtain high speed operation. Each of the field effect transistors is used as an on-off switches which has low impedance between the drain and source thereof when enabled and conducting. Outputs of the logic section are coupled to inputs of the latch section. Complementary clock signals are used to control the first and second field effect transistors so that one of the logic and latch section is enabled at a time. The logic section uses a two level emitter coupled tree configuration in order to increase logic capability. The use of the field effect transistors facilitates the use of a power supply having a voltage level of +3.6 volts. This is contrasted with the typical +5 volt supply used with conventional emitter coupled tree configurations. Accordingly, high speed at reduced power dissipation is achieved using the inventive process and hold system.

REFERENCES:
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patent: 4617475 (1986-10-01), Reinschmidt
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patent: 4963767 (1990-10-01), Sinh
patent: 5027005 (1991-06-01), Kitsuta et al.
patent: 5124589 (1992-06-01), Shiomi et al.
patent: 5134312 (1992-07-01), Jones, Jr. et al.
patent: 5170079 (1992-12-01), Komatsu et al.

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