High speed bipolar digital logic gate architecture

Details High speed bipolar digital logic gate architecture High speed bipolar digital logic gate architecture

1991-12-11

1993-07-20

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, H03K 19013, H03K 19016

Patent

active

052296610

ABSTRACT:
A current mode (NOR) logic circuit includes a first, fixed reference current source transistor stage coupled in circuit between a first voltage supply terminal and an input current node. A second, variable current source transistor stage is coupled in circuit between the first voltage supply terminal and the input current node. The second, variable current source supplies a variable quantity of auxiliary current to the input current node in dependence upon whether the input node sees a high logical level current or a low logic level current. The magnitude of the auxiliary current is such that the total of the auxiliary current and the prescribed reference current balances the input current being supplied to the input current node. A current switch transistor has its collector-emitter current flow path coupled in circuit between the first current source and one or more output current transistors. Base biasing of the current source transistors and the current switch transistor is independent of the power distribution bus for the overall system architecture in which the NOR gate is employed, so that the operations of the transistor stages are effectively immune to current transients on the power distribution bus. In addition, the bias voltages are such as to prevent transistor stages from operating in a saturation condition for either of the first and second input current levels, so that the speed-power product of the logic circuit is increased.

REFERENCES:
patent: 4210830 (1980-07-01), Fukahori
patent: 4623802 (1986-11-01), Cline et al.
patent: 4845387 (1989-07-01), Ovens

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