High speed bipolar D latch circuit with reduced latch clocking o

Details High speed bipolar D latch circuit with reduced latch clocking o High speed bipolar D latch circuit with reduced latch clocking o

1995-06-07

1996-07-30

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327222, 327212, 327202, H03K 3037, H03K 326

Patent

active

055415458

ABSTRACT:
A high speed bi-polar D latch circuit uses cross-coupled current-biased buffering transistors to block control current from output resistors so that the clock and data controls are not connected directly to the outputs of the latch. The memory cell portion of the latch which controls the latch output is constantly biased. Latch output swing is minimally affected by clock/data switching due to the buffering action of the emitter followers on the latch outputs. Changing the latch state is accomplished by changing the base-emitter voltage of the buffering transistors through the emitter followers. The circuit provides greater noise immunity at latch outputs during clock transitions and faster rise/fall times of output waveforms.

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