High-speed binary synchronous counter with precomputation of car

Details High-speed binary synchronous counter with precomputation of car High-speed binary synchronous counter with precomputation of car

1997-07-30

1999-08-31

Wambach, Margaret R.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular transfer means

377116, 377119, H03K 2116

Patent

active

059463694

ABSTRACT:
An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic circuit. The given counter stage includes a selection circuit for selecting one of two precomputed values for application to an input of a storage element in that stage based on a value of the carry-in signal. The selection circuit may include a two-input multiplexer for each of the N/K storage elements of the given counter stage. The jth multiplexer includes a first input coupled to an output of the jth storage element, and a second input coupled to an output of a logic circuit. The logic circuit generates a logic function based on the output of the jth storage element and other lower significant storage elements in the stage. The carry-in signal is applied as a select signal to the multiplexer and is used to select which of the two multiplexer inputs will be applied as the data input of the storage element. This selection of one of two precomputed values for application to a storage element input results in the counter having a critical path delay which is substantially independent of N.

REFERENCES:
patent: 4611337 (1986-09-01), Evans
patent: 4759043 (1988-07-01), Lewis
patent: 5381453 (1995-01-01), Chan
patent: 5559844 (1996-09-01), Lee
patent: 5754615 (1998-05-01), Colavin

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