High speed binary and binary coded decimal adder

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364787, G06F 750

Patent

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041387317

ABSTRACT:
A high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each composed of a half adder for generating a bit generate signal and a bit propagate signal, a binary mode carry look ahead input signal generator circuit part, a binary coded decimal mode carry look ahead input signal generator circuit part, an intermediate adder part and a full adder part. The high speed binary and binary coded decimal adder is capable of providing the result of an addition at a speed corresponding to six to seven logical stages.

REFERENCES:
patent: 3711693 (1973-01-01), Dahl
patent: 3805045 (1974-04-01), Larsen
patent: 3925651 (1975-12-01), Miller
patent: 3991307 (1976-11-01), Peddle et al.

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