High-speed binary adder

Details High-speed binary adder High-speed binary adder

1998-07-13

2001-01-16

Malzahn, David H. (Department: 2787)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S710000

Reexamination Certificate

active

06175852

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to a binary adder. Still more particularly, the present invention relates to a high-speed carry-lookahead binary adder.
2. Description of the Prior Art
Binary adders having a carry-lookahead are well known in the art. This type of binary adder is able to add two multiple-bit binary numbers while simultaneously computing a carry signal for each bit.
In order to compute the sum of two multiple-bit binary numbers A and B, a generate signal and a propagate signal are initially produced at each bit location. The equation for a generate signal G(i) is G(i)=A(i)B(i), and the equation for propagate signal P(i) is P(i)=A(i){overscore (B(i))}+{overscore (A(i))}B(i) or A(i)
B(i), where i denotes a bit location within the binary umbers having bit
0
as the most significant bit. These generate signals and propagate signals are then utilized to produce a carry signal for each bit. The generalized equation for a carry signal C(i) is C(i)=G(i)+P(i)G(i+1)+P(i)P(i+1)G(i+2)+P(i)P(i+1)P(i+2)G(i+3)+ . . . , etc.
The present disclosure provides an improved binary adder capable of producing group generate signals and group propagate signals with fewer levels of logic than is required by the prior art.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits and multiple eight-bit group propagate circuits. Each of the eight-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the eight-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.
All features and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 4764886 (1988-08-01), Yano
patent: 5140546 (1992-08-01), Ishikawa et al.
patent: 5500813 (1996-03-01), Song et al.
patent: 5964827 (1999-10-01), Ngo et al.

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