High speed BiCMOS conditional sum adder

Details High speed BiCMOS conditional sum adder High speed BiCMOS conditional sum adder

1991-04-15

1992-11-10

Nguyen, Long T.

Boots, shoes, and leggings

307446, G06F 750, H03K 1902

Patent

active

051630206

ABSTRACT:
An N-bit conditional sum adder 8 includes first and second conditional sum adders 10a and 10b. Each of the adders may be built from a plurality of one-bit conditional sum adders 110. In one embodiment, each one-bit adder 110 comprises a XNOR gate 50, a XOR gate 52, a NAND gate 54 and a NOR gate 56. The carry outputs CO.sub.a and CO.sub.b of the first conditional sum adder 10.sub.a are coupled to BiCMOS drivers 12 and 14 which in turn are coupled to the select inputs of a plurality of multiplexers 16 and 18. The multiplexers may be CMOS multiplexers built from transmission gates.

REFERENCES:
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patent: 4918640 (1990-04-01), Heimsch et al.
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patent: 5047976 (1991-09-01), Goto et al.
Rothermel et al., "Realization of Transmission-Gate Conditional-Sum (TGCS) Adders with Low Latency Time", IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 558-561.
J. Sklansky, "Conditional-Sum Addition Logic", IRE Transactions on Electronic Computers , Jun. 1960, pp. 226-231.
Gallia et al, "BiCMOS ASIC for High Performance Systems", pp. 1-4 May 1990.

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