Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Patent
1997-11-06
2000-06-06
Geckil, Mehmet B.
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
709230, G06F 1516
Patent
active
06073180&
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a high speed batch file transfer method, apparatus, and storage medium storing a program for executing said transfer method which are suitable for use in conducting communication between personal computers, work stations, various communication terminals and the like of devices which are connected in a network.
2. Background Art
Accompanying the development in the multi-media era, there exists an increasing demand for services which deliver large amounts of bulk data such as images and the like to user terminals from a server. With the current VOD (Video On Demand), due to the extreme increase in not only the transfer start orders of the file, but also control orders, e.g., pause, rewind and the like, which contribute to the load on the server processor, it is not possible to sufficiently appreciate the merits from the increased speed of the network. In contrast, for the sake of user convenience and economics, a system is being considered in which a large amount of bulk data corresponding to a single CD-ROM or movie is transmitted to a user storage medium in a few seconds to a few tens of seconds, followed by instant release of the network. The present invention provides a method and apparatus for achieving the aforementioned; the various components comprising the background of the present invention will be explained in detail below with reference to the figures.
FIG. 20A is a diagram showing the architecture of a general purpose computer equipped with an ATM network adapter card. FIG. 20B is a diagram showing the data flow at the time of receiving a large capacity file using a file transfer protocol. The file transfer protocol (ftp) is an application placed onto an internet protocol (TCP/IP) which is processed as software by means of a host CPU (central processing unit) of a computer containing the TCP/IP.
In addition, FIG. 21 shows a protocol stack of a file transfer protocol (ftp) in the case when using an ATM (Asynchronous Transfer Mode) link with the execution hardware written along side. TCP, IP and SNAP/LLC represent abbreviations for "transmission control protocol", "internet protocol" and "subnetweork access point/logical link control", respectively. In addition, AAL, SAR, PHY and S/P conversion are likewise abbreviations for "ATM adaptation layer", "segmentation and reassembly sublayer", "physical protocol" and "serial/parallel conversion", respectively.
Here, the action at the time of receiving a large capacity file using a file transfer protocol will be explained. Furthermore, the actions for transmission (sending) are identical with the sequence being simply reversed, and thus an explanation will be omitted. The data sent from the computer network E10 of ATM-LAN (Local Area Network) or the like is first received by ATM adapter card E5, and a physiological layer is terminated by means of a cell synchronized chip which is passed on to the ATM layer chip as 53-byte cell data to terminate the ATM layer.
Accordingly, in the ATM layer, separation by VCI/VPI (Virtual Path Identifier/Virtual Channel Identifier) and various processing are performed. According to the ALL layer (standard type 5), by means of a SAR chip, 48-byte information (SAR-PDU (Protocol Data Unit)) from which the cell header has been removed is linked, and CRC chip (Cyclic Redundancy Check) and data long check are conducted to form a CPCS (Convergence Sublayer Common Part)-PDU payload (see FIG. 20B). The CPCS-PDU payload is transferred as user data to the host CPU.cndot.E1 via a high speed general purpose bus (a PCI (Peripheral Component Interconnect Bus) is used here) and PCI bridge E4.
IP datagram is formed from the data sent to the host CPU.cndot.E1, and the CPU then sequentially terminates an IP layer, following which the core of the encapsulated file transfer data is fetched. Host CPU.cndot.E1 subsequently stores the core of the fetched transfer data in a hard disk E6 via PCI bus E3.
Further, in FIG. 20A, E30 is a CRT (Cathode-Ray T
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Kotabe Satoshi
Onoda Tetsuya
Yoshikawa Taro
Geckil Mehmet B.
Nippon Telegraph and Telephone Corporation
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