High speed asynchronous data interface

Details High speed asynchronous data interface High speed asynchronous data interface

1990-03-14

1991-09-17

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

307516, 375110, H04L 7033

Patent

active

050501941

ABSTRACT:
A digital data interface for high speed asynchronous data transfer is described. The design is nominally intended for integration onto the component chips in communications systems. The system is described with respect to its realization in CMOS IC technology. The techniques involved, however, may easily be applied to other technologies. The interface employs Manchester Bi-Phase Mark encoding of the clock and data to allow extraction of the clock and data signals at the receiver. Furthermore, use of this Manchester code allows code violations to be easily employed as frame markers for synchronization means. The essence of the clock extraction and data detection circuit is the use of calibrated delay line elements to suppress data transitions within the coded input signal, thus allowing the clock transitions to be detected from which the clock is then generated.

REFERENCES:
patent: 4592072 (1986-05-01), Stewart
patent: 4611335 (1986-09-01), Arai et al.
patent: 4752942 (1988-06-01), Iwakami
patent: 4805197 (1989-02-01), Jagt et al.

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