High speed arithmetic and logic generator with reduced complexit

Details High speed arithmetic and logic generator with reduced complexit High speed arithmetic and logic generator with reduced complexit

1990-10-10

1993-11-23

Mai, Tan V.

Boots, shoes, and leggings

307464, G06F 750

Patent

active

052650448

ABSTRACT:
A technique for generating a carry, AND, OR, NAND, NOR, INVERTING logic and sum and carry: operation in a one or at most two device delay by employing negative differential resistance devices. Circuits implemented with this technique are not only extremely fast, but use a small number of active devices as well. This technique could be implemented in building circuits using any transistor Bipolar Transistors, Field Effect Transistors (FETs), High Electron Mobility Transistors (HEMTs), Hetero-junction Bipolar Transistors (HBTs), etc. The negative differential resistance characteristics of the resonant tunneling transistor can be exploited to increase the noise margin. Resonant tunneling devices have the added advantage of working at very high speeds, and could yield propagation delays less than 5ps.

REFERENCES:
patent: 3113206 (1963-12-01), Harel
patent: 3155839 (1964-11-01), Modiano
patent: 3609329 (1969-05-01), Martin
patent: 4423339 (1983-12-01), Seelbach et al.
patent: 4787047 (1988-11-01), Wei

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