Static information storage and retrieval – Associative memories
Reexamination Certificate
2007-03-13
2008-09-09
Nguyen, Viet Q (Department: 2827)
Static information storage and retrieval
Associative memories
C365S202000, C365S189070, C365S185080, C365S049110, C365S049170
Reexamination Certificate
active
07423895
ABSTRACT:
A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.
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Nojima Isao
Sarin Vishal
Tran Hieu Van
DLA Piper (US) LLP
Nguyen Viet Q
Silicon Storage Technology, Inc.
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