High speed and low parasitic capacitance semiconductor...

Details High speed and low parasitic capacitance semiconductor... High speed and low parasitic capacitance semiconductor...

2001-02-26

2002-08-20

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Forming base region of specified dopant concentration profile

C438S320000, C438S366000, C257S198000, C257S588000

Reexamination Certificate

active

06436781

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a high speed and low parasitic capacitance semiconductor device including a vertical transistor and a heterojunction bipolar transistor, and a method for fabricating such the device.
2. Description of the Related Art
A high speed bipolar transistor may be realized by increasing cut-off frequency f
T
as well as reducing the parasitic capacitance and parasitic resistance. A typical parasitic capacitance includes collector-base capacitance C
CB
. A pn junction capacitance per unit junction area may be determined almost with a relatively lower one between impurity concentrations in p-type and n-type regions. Thus, capacitance C
CB
can be determined in accordance with a design for the collector concentration. When focusing attention only on the parasitic capacitance, therefore, it is desirable to reduce the collector concentration as low as possible.
On the other hand, however, the collector capable of improving cut-off frequency f
T
may have a relatively higher concentration to prevent the electric field from decreasing inside the depletion layer between the collector and base at high current operation. Thus, the contrary requests must be satisfied at the same time.
Any conventional technology has not responded such the requests and still includes the following disadvantages. A base region on which an emitter is formed directly is hereinafter referred to as an intrinsic base and a peripheral region thereof is called an outer base region.
FIG. 24
is a vertical cross sectional view showing a semiconductor device according to a first related art. The device includes p type silicon substrate
1
, n
+
buried layer
2
a
, adjacent p
+
buried layer
2
b
, epitaxial silicon collector layer
3
, silicon oxide
4
formed by LOCOS (local oxidation of silicon) and collector lead-out region
5
. The device also includes silicon oxide
6
, polysilicon base electrode
7
, silicon oxide
8
, outer base region
10
, intrinsic base
11
, second collector region
12
, polysilicon emitter electrode
13
and single crystalline emitter region
14
. The device further includes silicon oxide
15
, aluminum alloy emitter electrode
16
a
, aluminum alloy base electrode
16
b
, aluminum alloy collector electrode
16
c
, first aperture
101
, second aperture
102
and third aperture
103
.
A vertical bipolar transistor is fabricated with emitter
14
, intrinsic base
11
and second collector
12
, in the above semiconductor device, which are lead out through the electrodes isolated by silicon oxides
6
,
8
and
15
.
Second collector
12
located directly beneath outer base
10
has a high collector concentration equal to that of the region directly beneath intrinsic base
11
in this semiconductor device. Whereas the high speed may be achieved to a certain extent, therefore, the collector-base capacitance intends to increase.
FIG. 25
is a vertical cross sectional view showing another semiconductor device according to the first related art. Description for the same portions as those in
FIG. 24
may be omitted in
FIG. 25
with giving the same reference numerals. Note that a feature of collector
12
greatly differs from that in FIG.
24
.
The collector concentration directly beneath outer base
10
in the semiconductor device is controlled lower than that of the region directly beneath intrinsic base
11
. However, low concentration collector region
3
is interposed between high concentration collector region
12
directly beneath intrinsic base
11
and n
+
buried layer
2
a
. Therefore, cut-off frequency f
T
may decrease even if the collector-base capacitance is small.
FIG. 26
is a vertical cross sectional view showing a semiconductor device according to a second related art. The device includes p type silicon substrate
1
, n
+
buried layer
2
a
, adjacent p
+
buried layer
2
b
, epitaxial silicon collector layer
3
, LOCOS silicon oxide
4
and collector lead-out region
5
. The device also includes silicon oxide
6
, polysilicon base electrode
7
, silicon oxide
8
, outer base
10
, intrinsic base
11
, second collector region
12
, polysilicon emitter electrode
13
and single crystalline emitter region
14
. The device further includes silicon oxide
15
, aluminum alloy emitter electrode
16
a
, aluminum alloy base electrode
16
b
and aluminum alloy collector electrode
16
c.
A vertical bipolar transistor is fabricated with emitter
14
, intrinsic base
11
and second collector
12
, in the above semiconductor device, which are lead out through the electrodes isolated by silicon oxides
6
,
8
and
15
.
In this structure, single crystalline base
11
is epitaxially grown whole over Si collector region
12
. Whereas there is no region called outer base
10
, a portion directly beneath the emitter may be considered as the intrinsic base. Thus, the collector located direct beneath a peripheral base region of the intrinsic base may also have a high concentration.
FIG. 27
is a vertical cross sectional view showing a semiconductor device according to a third related art. The device includes p-silicon substrate
1
, n
+
buried layer
2
a
, adjacent p
+
buried layer
2
b
, epitaxial silicon collector layer
3
, LOCOS silicon oxide
4
and collector lead-out region
5
. The device also includes a silicon oxide
6
, polysilicon base electrode
7
, silicon oxide
24
, intrinsic base
11
, single crystalline Si intrinsic base layer
21
, polycrystalline Si layer
22
, single crystalline emitter region
23
and silicon oxide
25
. The device further includes second collector region
12
, polysilicon emitter electrode
13
, silicon oxide
15
, aluminum alloy emitter electrode
16
a
, aluminum alloy base electrode
16
b
and aluminum alloy collector electrode
16
c
. The device also includes aperture
201
for making silicon oxide
6
contact with single crystalline Si intrinsic base layer
21
and polycrystalline Si layer
22
, and aperture
202
for making polysilicon emitter electrode
13
and single crystalline emitter region
23
contact with intrinsic base
21
and polycrystalline Si layer
41
.
Whereas aperture
202
must be formed by aligning with previously formed aperture
201
in the first and second related arts, the aperture may only be formed once according to the third related art, whereby miniaturization of the transistor may be achieved.
The above-described related arts, however, can not realize both the low collector concentration for reducing the parasitic capacitance and the high collector concentration for improving the cut-off frequency f
T
simultaneously.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of satisfying the contrary requests to achieve both the low collector concentration for reducing the parasitic capacitance and the high collector concentration for improving cut-off frequency f
T
simultaneously.
The present invention is provided with a method for fabricating a semiconductor device comprising the steps of: forming a silicon material having a high concentration buried layer and a low concentration surface region; forming a single layer or multi-layered film on the surface of the silicon material; opening an aperture in the film by means of photolithography and dry etch; implanting phosphorous ions into the silicon material to form a first collector region adjacent to the buried layer before removing the photoresist; implanting boron ions into the surface of the silicon material to form an intrinsic base; implanting phosphorous ions selectively into the silicon material to form a second collector region between the intrinsic base and the first collector region with using the film used to form the aperture as the mask; and disposing a polysilicon emitter electrode for diffusing the dopant from the polysilicon emitter electrode into the intrinsic base region to form a single crystalline emitter region.
The present invention is also pro

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