High speed and low cost SDRAM memory subsystem

Details High speed and low cost SDRAM memory subsystem High speed and low cost SDRAM memory subsystem

1997-08-21

1999-04-20

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365189, G11C 800

Patent

active

058963464

ABSTRACT:
A synchronous dynamic random access memory subsystem includes two banks of connectors for receiving single or dual in-line memory modules. A clock is located in close proximity to the connectors and produces clock pulses having a known rise time. Clock wiring is placed between the clock and the connectors, and module wiring carries the clock pulses from the connectors to the memory. The wiring has an impedance and length such that the round trip delay time of clock pulses between the clock and the memory is less than the rise time of the clock pulses. The clock is preferably located between the two banks of connectors to reduce wiring length to a minimum and minimize coupled noise.

REFERENCES:
patent: 4813014 (1989-03-01), DeBell
patent: 4958322 (1990-09-01), Kosugi et al.
patent: 5164916 (1992-11-01), Wu et al.
patent: 5272664 (1993-12-01), Alexander et al.
patent: 5278801 (1994-01-01), Dresser et al.
patent: 5341486 (1994-08-01), Castle
patent: 5357624 (1994-10-01), Lavan
patent: 5513135 (1996-04-01), Dell et al.
patent: 5533194 (1996-07-01), Albin et al.
patent: 5721860 (1998-02-01), Stolt et al.

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