High-speed and high-precision phase locked loop having phase det

Details High-speed and high-precision phase locked loop having phase det High-speed and high-precision phase locked loop having phase det

1998-06-16

2000-12-05

Pascal, Robert

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 8, H03L 700

Patent

active

061572632

ABSTRACT:
A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal. A third p FET has a gate coupled to the drain of the second p FET. A second n FET has a source coupled to the drain of the third p FET for providing the up signal, and has a gate for receiving the reference clock signal. A third n FET has a source coupled to the drain of the second n FET and has a gate coupled to the gate of the third p FET. The down signal generator includes a fourth p FET having a gate for receiving the set signal. A fifth p FET has a source coupled to the drain of the fourth p FET and has a gate for receiving a VCO clock signal. A fourth n FET has a source coupled to the drain of the fifth n FET and has a gate for receiving the set signal. A sixth p FET has a gate coupled to the drain of the fifth p FET. A fifth n FET has a source coupled to the drain of the sixth p FET and has a gate for receiving the VCO clock signal. A sixth n FET has a source coupled to the drain of the fifth n FET for providing the down signal, and has a gate coupled to the gate of the sixth p FET. A reset circuit, such as a NAND gate, has a first input coupled to the drain of the third p FET, has a second input coupled to the drain of the sixth p FET, and has an output for generating the set signal.

REFERENCES:
patent: 5317283 (1994-05-01), Korhonen
patent: 5373255 (1994-12-01), Bray et al.
patent: 5896066 (1999-04-01), Katayama et al.

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