High speed and high efficiency layout for dram circuits

Details High speed and high efficiency layout for dram circuits High speed and high efficiency layout for dram circuits

1985-07-11

1987-10-13

Hecker, Stuart N.

Static information storage and retrieval

Format or disposition of elements

365207, 365208, G11C 502, G11C 700, G11C 702

Patent

active

047003286

ABSTRACT:
A dynamic random access memory (DRAM) array combining metal word lines and folded bit line architecture. Multiplexed switching of the bit lines is utilized to make connection to the sense amps. The word lines connect to every fourth access transistor in a column with twice as many word lines employed as in prior art arrays. The use of folded bit lines reduces the effects of noise on bit line sensing while the metal word lines increase speed by several orders of magnitude. The sense amps are disposed between blocks of memory cells and sense every other bit line. Column decoders are placed between rows of sense amps with row decoders and drivers at the end of the blocks of cells.

REFERENCES:
patent: 4449207 (1984-05-01), Kung et al.
patent: 4476547 (1984-10-01), Miyasaka
patent: 4481609 (1984-11-01), Higuchi et al.
patent: 4493056 (1985-01-01), Mao
patent: 4586171 (1986-04-01), Fujishima

Affiliated with

Also associated with

Rating

High speed and high efficiency layout for dram circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed and high efficiency layout for dram circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed and high efficiency layout for dram circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-416063