Static information storage and retrieval – Addressing – Sync/clocking
Patent
1994-11-17
1995-09-05
Popek, Joseph A.
Static information storage and retrieval
Addressing
Sync/clocking
36523008, 327 14, G11C 800
Patent
active
054485290
ABSTRACT:
An address transition detection (ATD) circuit provides an address transition detection pulse in response to either a high-to-low or low-to-high external address transition. The ATD circuit includes an address buffer that translates an externally applied address signal into an internal address signal and its logical complement. Two delay chains, each of which includes inverters, capacitors, a NAND gate and a CMOS pass gate, combine with the address buffer and an n-channel pull-down transistor to provide the ATD circuit. The outputs of the CMOS pass-gates are connected to the gate of the pull-down transistor. The drain of the pull-down transistor serves as the local ATD node of a dual-load feed-back controlled ATD pulse generator. The ATD local node is common to address buffers that select memory cells within a particular memory block. Address buffers responsible for switching between blocks have separate feedback-controlled ATD pulse generators in order to optimize the access time of the memory device.
REFERENCES:
patent: 4592028 (1986-05-01), Konishi
patent: 4787068 (1988-11-01), Kihara
Medhekar Ajit
Reddy Chitranjan N.
Alliance Semiconductor Corporation
Popek Joseph A.
LandOfFree
High speed and hierarchical address transition detection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed and hierarchical address transition detection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed and hierarchical address transition detection circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-478526