High speed analog to digital converter, decimation and storage s

Details High speed analog to digital converter, decimation and storage s High speed analog to digital converter, decimation and storage s

1995-08-31

1998-04-28

Elmore, Reba I.

Boots, shoes, and leggings

341126, 341155, G06F 1717, H03M 100, H03M 112

Patent

active

057453942

ABSTRACT:
A high speed analog to digital sampling system. The invention allows for decimation and optimal storage of samples from an interleaved analog to digital conversion system. The circuit architecture provides for switchable flip-flops at the outputs of a set of interleaved analog to digital converters. Decimation is accomplished by only activating a selection of the analog to digital converters within the set of interleaved analog to digital converters. The flip-flops associated with the inactive analog to digital converters are configured to form a shift register. The samples of the activated analog to digital converters are shifted into the shift register. When all the flip-flops of the shift register are full, the samples are written to memory of the system. The shift register configuration allows the samples to be stored so that the allocation of system memory is optimized and the number of system memory writes is reduced. One embodiment of the invention includes presettable dividers for providing control over the rate at which the flip-flops are loaded with sampled data.

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patent: 5206944 (1993-04-01), Pilkenton
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