High speed analog-to-digital converter and digital-to-analog...

Details High speed analog-to-digital converter and digital-to-analog... High speed analog-to-digital converter and digital-to-analog...

1999-12-20

2002-11-05

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S126000

Reexamination Certificate

active

06476749

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to analog-to-digital and digital-to-analog converters, and is especially applicable to high speed analog-to-digital converters for wireless communications.
2. Background Art
High speed analog-to-digital converters and digital-to-analog converters are used in wireless telecommunications systems, where digital receivers are preferred, for high speed instruments, for example oscilloscopes, and for various other applications. Typically, an analog-to-digital converter comprises a clock-driven sample-and-hold circuit, which samples the analog signal at intervals and holds the sample values, and a quantizer which converts each quantized sample into a digital numerical representation. Typically, the quantizer will compare the ample value with a number of different voltage thresholds in order to determine the value of the sample to within a fairly small band and represent it digitally. It is desirable to provide high resolution as well as high speed, but these tend to be incompatible. Higher resolutions entail more comparisons, i.e. with a larger number of discrete voltage thresholds, which will increase the processing time required to perform the calculations.
One of the fastest A/D converters, known as the “Flash ADC”, applies the sample value to a bank of comparators, each of which compares it with a different reference or threshold value. The outputs of the bank of comparators are applied to a Gray code decoder. Unfortunately, such Flash A/D converters require a ladder network of accurate resistors, preferably laser-trimmed, and so are expensive to produce. Consequently, most high speed devices presently available commercially have limited resolution are able to digitize a 500 MHz analog signal. Current applications, however, may require conversion of signals at 1 GHz and higher.
In order to convert higher frequency signals, it has been proposed to time-interleave two or more such high speed A/D converters. In a paper entitled “Time Interleaved Converter Arrays”, IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 6, December 1980, William C. Black, Jr., et al, disclosed a time interleaved A/D converter which used four sample-and-hold circuits and four quantizers and a multiplexer to obtain analog-to-digital conversion of an analog signal having a frequency four times that of the signal handled by each converter. In a paper entitled “A 1-GHz 6-bit ADC System”, IEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, December 1987, Ken Poulton et al disclosed a time-interleaved analog-to-digital converter capable of a sampling rate of one Gigasample per second using four sample-and-hold circuits and four quantizers. However, instead of a multiplexer, Poulton et al's converter used four memory banks read sequentially. In both cases, the time-interleaved converter arrays used offset clock signals for the four different sample-and-hold circuits. Black et al's multiplexer and Poulton et al's memory readout, however, operated at the speed of the system clock which was four times the speed of the individual sample-and-hold clock signals. Consequently, the sample-and-hold circuits operated at only one quarter of the overall sampling rate. A disadvantage of sitch time-interleaved converters is that phase jitter is produced because the offset clock signals are not precisely 90 degrees out of phase with each other, and errors arise because of variations in the high-speed clock which operates the multiplexer or memory readout. Also, the sample-and-hold circuits each see the full wideband signal, which places limitations on their capabilities.
The problem of obtaining both high speed and high resolution has been addressed by a number of people. In a paper entitled “High Speed AID Conversion Using QMF Banks”, Proceedings of IEEE International Symposium on Circuits and Systems (1990), Petraglia et al disclosed a technique for performing A/D conversion using quadrature mirror filter banks. Petraglia et al used an analysis filter bank which comprised a bank of switched capacitance filters and a bank of downsamplers. The downsampled subband signals were converted by a bank of A/D converter units and then applied to a synthesis filter bank which comprised a bank of upsamplers and a bank of digital filters. Although Petraglia et al's approach avoids the need for offset clock signals, and hence avoids the phase jitter problem, it is not entirely satisfactory because it uses switched capacitance filters. Discrete time-switched capacitance filters limit the speed and introduce switching noise, reducing signal-to-noise ratio. Reducing signal-to-noise ratio reduces resolution.
U.S. Pat. No. 5,568,142 issued Oct. 22, 1996 (Velazquez et al), disclosed an A/D converter using an analog analysis filter bank and a digital synthesis filter bank. The use of an analog (continuous time) analysis filter bank avoids the problems associated with discrete time switched capacitor filters. However, with present technology, it would be extremely difficult to achieve 1 Gigasample per second conversion rates with the analog-to-digital converter disclosed by Velazquez et al. In particular, Velazquez et al use several 64 tap digital filters in the synthesis filter bank. Hence, with a rate of 1 Gigasample per second, each digital filter would have to perform 65×10
9
multiplication operations per second and 64×10
9
addition operations per second. With current technology, this number of operations is not feasible.
SUMMARY OF THE INVENTION
The present invention seeks to eliminate, or at least mitigate, the disadvantages of these known analog-to-digital converters.
According to one aspect of the present invention, there is provided an analog-to-digital converter for converting an analog input signal (u(t)) having a frequency up to a predetermined maximum frequency (F
max
) to a digital output signal (x(n)) having a predetermined output sampling rate (F
s
) equal to at least double the maximum frequency (F
max
), the analog-to-digital converter comprising a plurality of analog narrowband filters (F
0
-F
M−1
; F
L
,F
H
,F
P
) for filtering the analog input signal (u(t)) to produce a corresponding plurality of narrowband signals (X
0
-X
M−1
; X
L
,X
H
,X
P
,), each narrowband filter having a passband, the sum of the gains of the narrowband filters at any frequency within the passbands of the plurality of narrowband filters being substantially unity, a corresponding plurality of sample-and-hold devices (SH
0
-SH
M−1
; SH
L
,SH
H
,SH
P
) clocked by a plurality of clock signals (&phgr;
0
-&phgr;
M−1
; &phgr;
1
, &phgr;
2
), respectively, each of the plurality of clock signals having a frequency at least double the bandwidth of the corresponding narrowband filter, and a plurality of quantizers (Q
0
-Q
M−1
) each connected to a respective one of the sample-and-hold devices (SH
0
-SH
M−1
) and operable to provide a digitized value of each sample held by the corresponding sample-and-hold device, the converter further comprising sampling and summing means (12,R
0
-R
M−1
; 12
1
,12
2
,14; 12,14
1
,14
2
; R
L
,R
H
,R
P
) for sampling and summing the outputs of the quantizers to produce said digital output signal (x(n)), the sampling being carried out sequentially at the predetermined sampling rate (Fs) in response to an output clock signal (CLK; &phgr;
2
), the frequencies and phase-relationships of the plurality of clock signals (&phgr;
0
-&phgr;
M−1
; &phgr;
1
,&phgr;
2
,&phgr;
3
) being such that each sample point of the output clock signal (CLK; &phgr;
2
) coincides with a sample point of one of the plurality of clock signals (&phgr;
0
-&phgr;
M−1
; &phgr;
1
,&phgr;
2
; &phgr;
1
,&phgr;
2
,&phgr;
3
)
In one preferred embodiment of the invention, the plurality of narrowband filters all have the same bandwidth equal to one half of the predetermined output sampling rate (Fs) divided by the number (M) of said narrowband signals, and the plurality of clock signals (&phgr;
0
-&phgr;
M&minus

Affiliated with

Also associated with

Rating

High speed analog-to-digital converter and digital-to-analog... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed analog-to-digital converter and digital-to-analog..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed analog-to-digital converter and digital-to-analog... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2975694