High speed analog to digital converter

Details High speed analog to digital converter High speed analog to digital converter

2003-01-23

2004-01-06

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06674388

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a Continuation-in-Part of Application Ser. No. 10/460,622 Filed: May 24, 2002, Titled: DISTRIBUTED AVERAGING ANALOG TO DIGITAL CONVERTER TOPOLOGY, Inventors: MULDER et al. and is related to Application Ser. No. 10/158,774, Filed: May 31, 2002; Titled: ANALOG TO DIGITAL CONVERTER WITH INTERPOLATION OF REFERENCE LADDER, Inventors: MULDER et al. Application Ser. No. 10/158,193, Filed: May 31, 2002, Titled: CLASS AB DIGITAL TO ANALOG CONVERTER/LINE DRIVER, Inventors: Jan MULDER et al. and Application Ser. No. 10/158,733, Filed: May 31, 2002, Inventor: Jan MULDER; Titled: SUBRANGING ANALOG TO DIGITAL CONVERTER WITH MULTI-PHASE CLOCK TIMING, Inventors: van der GOES et al. all of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to analog to digital converters (ADC's), and more particularly, to reducing nonlinearities and inter-symbol interference in high-speed analog to digital converters.
2. Related Art
A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC's (i.e. high speed, low power, low area, high resolution).
FIG. 1
shows a generic two-step subranging architecture, comprising a reference ladder
104
, a coarse ADC
102
, a switching matrix
103
, a fine ADC
105
, coarse comparators
107
, fine comparators
108
and an encoder
106
. In most cases, a track-and-hold
101
is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC
102
. The coarse ADC
102
compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix
103
connects the fine ADC
105
to a subset of the reference voltages (called a “subrange”) that is centered around the input signal voltage.
Modem flash, folding and subranging analog to digital converters (ADC's) often use averaging techniques for reducing offset and noise of amplifiers used in the ADC. One aspect of averaging is the topology that is used to accomplish averaging, i.e., which amplifier outputs in which arrays of amplifiers are averaged together.
In general, flash, folding and subranging ADC's use cascades of distributed amplifiers to amplify the residue signals before they are applied to the comparators. These residue signals are obtained by subtracting different DC reference voltages from an input signal V
in
. The DC reference voltages are generated by the resistive ladder (reference ladder)
104
biased at a certain DC current.
High-resolution ADC's often use auto-zero techniques, also called offset compensation techniques, to suppress amplifier offset voltages. In general, autozeroing requires two clock phases (&phgr;
1
and &phgr;
2
). During the auto-zero phase, the amplifier offset is stored on one or more capacitors, and during the amplify phase, the amplifier is used for the actual signal amplification.
Two different auto-zero techniques can be distinguished, which are illustrated in
FIGS. 2 and 3
. The technique shown in
FIG. 2
connects an amplifier
201
in a unity feedback mode during the auto-zero clock phase &phgr;
1
. As a result, a large part of the amplifier
201
input offset voltage is stored on input capacitors C
1
a
, C
1
b
. The remaining offset is stored on output capacitors C
2
a
, C
2
b
if available.
The second technique, shown in
FIG. 3
, shorts the amplifier
201
inputs during the auto-zero phase &phgr;
1
and connects them to a DC bias voltage V
res
. Here, the amplifier
201
output offset voltage is stored on the output capacitors C
2
a
, C
2
b
. Many ADC architectures use a cascade of several (auto-zero) amplifiers to amplify the input signal prior to applying to the comparators
107
,
108
. In general, flash, folding and subranging ADC's use arrays of cascaded amplifiers, and averaging and interpolation techniques are used to improve performance.
Unfortunately, the performance of cascaded arrays of amplifiers degrades significantly at high clock and input signal frequencies. The cause of this degradation is illustrated in
FIG. 4
when the reset technique shown in
FIG. 3
is used, and where R
SW
is shown as a circuit element, and the current flow I
C
is explicitly shown.
When the amplifier
201
is in the auto-zero phase &phgr;
1
, the input capacitors C
1
a
, C
1
b
are charged to the voltage V
sample
that is provided by the track-and-hold amplifier
101
. As a result, a current I
C
will flow through the input capacitors C
1
a
, C
1
b
and an input switch (not shown). Due to the finite on-resistance R
SW
of the input switch (see FIG.
4
), an input voltage is generated, which will settle exponentially towards zero. This input voltage is amplified by the amplifier
201
and results in an output voltage that also slowly settles towards zero (assuming the amplifier
201
has zero offset).
Essentially, the auto-zero amplifier
201
is in a “reset” mode one-half the time, and in an “amplify” mode the other one-half the time. When in reset mode, the capacitors C
1
a
, C
1
b
are charged to the track-and-hold
101
voltage, and the current I
C
flows through the capacitors C
1
a
, C
1
b
and the reset switches, so as to charge the capacitors C
1
a
, C
1
b.
When the ADC has to run at high sampling rates, there is not enough time for the amplifier
201
output voltage to settle completely to zero during the reset phase. As a result, an error voltage is sampled at the output capacitors C
2
a
, C
2
b
that is dependent on the voltage V
sample
. This translates into non-linearity of the ADC, and often causes inter-symbol interference (ISI).
The problem of ISI occurs in most, if not all, ADC architectures and various approaches exist for attacking the problem. The most straightforward approach is to decrease the settling time constants. However, the resulting increase in power consumption is a major disadvantage.
Another approach is to increase the time allowed for settling, by using interleaved ADC architectures. However, this increases required layout area. Furthermore, mismatches between the interleaved channels cause spurious tones. The ISI errors can also be decreased by resetting all cascaded amplifiers during the same clock phase. Unfortunately, this is not optimal for high speed operation either.
SUMMARY OF THE INVENTION
The present invention is directed to an analog to digital converter topology that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided an analog to digital converter including a reference ladder, a clock having phases &phgr;
1
and &phgr;
2
, and a track-and-hold amplifier tracking an input signal with its output signal during the phase &phgr;
1
and holding a sampled value during the phase &phgr;
2
. A plurality of coarse amplifiers each input a corresponding tap from the reference ladder and the output sign. A plurality of fine amplifiers input corresponding taps from the reference ladder and a signal corresponding to the output signal, the taps selected based on outputs of the coarse amplifiers. A circuit responsive to the clock receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the corresponding taps to the fine amplifiers during the phase &phgr;
2
and substantially rejecting the signal corresponding to the output signal during the phase &phgr;
2
. An encoder converts outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.
In another aspect of the present invention there is provided an analog to digital converter including a reference ladder and a two-phase clock having phases &phgr;
1
and &phgr;
2
. A track-and-hold amplifier tracking an input signal with its output signal during the phase &phgr;
1
and holding a sampled value during the phase (&phgr;
2
.

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