High speed analog to digital converter

Details High speed analog to digital converter High speed analog to digital converter

2000-10-17

2002-09-03

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C331S017000, C341S118000, C341S120000, C341S122000, C341S155000, C341S156000

Reexamination Certificate

active

06445329

ABSTRACT:

BACKGROUND
The invention generally relates to electrical circuit components. In particular, the invention relates to analog to digital converters.
Analog to digital converters (ADC) take analog electrical signals and convert them into a digital format. The ADC will sample the analog signal at a clocking rate and convert each sample into a digital output. The value of the digital output is based on the magnitude of the sample's voltage. Due to the increasing speeds of electrical circuitry, it is desirable to have faster ADCs.
One approach to making high speed ADCs uses bipolar technology. One drawback to bipolar technology is that it has higher power dissipation than complementary metal oxide semiconductor (CMOS) field effect transistor technology. Additionally, the signal to noise distortion ratio (SNDR) is not satisfactory for some applications. For example, a typical bipolar ADC using a five volt power supply, 50 megahertz (MHz) input frequency and ten bit resolution would dissipate four watts and would have a SNDR of 47 decibels (dB).
CMOS based ADCs typically have not had the resolution, such as only six to eight bits of resolution, compared to 10 bits or more of bipolar ADCs. The CMOS ADCs also use high power supply voltages, such as 3.3 volts to 10 volts. Such high power supply voltages are not compatible with some semiconductor technologies, such as 0.18 micrometer (um), or lower technology.
Some design approaches to improve CMOS ADCs have used single step parallel flash converters, which have resulted in larger chip areas and high power dissipation for these ADCs. Additionally, these CMOS ADCs have not had satisfactory SNDRs, which reduces the accuracy achieved by the higher resolution.
Accordingly, it is desirable to have alternate approaches to producing high speed ADCs.
SUMMARY
An analog to digital converter having several groups of range analysis blocks. Each range analysis block produces an output representative of a range of bits in a digital output of the analog to digital converter. The first range analysis block analyzes the analog signal in a coarse manner, and selects the appropriate reference voltage and offset voltage to pass to the next set of range analysis blocks, the next set of blocks analyzes the analog signal at a higher precision.


REFERENCES:
patent: 6011502 (2000-01-01), Kao
patent: 6069579 (2000-05-01), Ito et al.
patent: 6107949 (2000-08-01), Gross, Jr.
patent: 6292061 (2001-09-01), Qu

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