Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-11-14
2003-04-08
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S154000
Reexamination Certificate
active
06545623
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to analog to digital converter (hereinafter “ADC”) systems using dynamic element matching (or shuffling), such as capacitor or current source shuffling, and, more particularly, to a method and apparatus for providing such shuffling with improved efficiency.
BACKGROUND OF THE INVENTION
Many types of commercial ADCs exist. Two examples are the &Sgr;-&Dgr; type and the pipelined type. Many architectures exist for both types. In addition, within a number of such architectures for both types of ADCs, capacitor shuffling or current sink/source shuffling is provided in order to reduce capacitor or current sink/source mismatch distortion. A simple, second-order &Sgr;-&Dgr; converter with shuffling is shown in
FIG. 1
as an example to illustrate a conventional implementation of shuffling.
The converter includes a first analog summing node
1
, a first analog integrator
2
, a second analog summing node
3
, a second analog integrator
4
, a coarse ADC
5
, which is typically a flash ADC, a shuffler unit
6
and a digital to analog converter
7
. An analog signal V
IN
(X) is applied on an input node
8
to analog summing node
1
. The output of analog summing node
1
is provided as an input to analog integrator
2
. The output of analog integrator
2
is provided as an input to analog summing node
3
. The output of analog summing node
3
is provided as an input to analog integrator
4
. The output of analog integrator
4
is provided as an input to coarse ADC
5
. The output of coarse ADC
5
is provided on node
9
as an output of the &Sgr;-&Dgr; converter, and is provided as an input to shuffler unit
6
. The output of shuffler unit
6
is provided as an input to DAC
7
. The output of DAC
7
is provided to a subtracting input of summing node
1
and of summing node
3
.
The feedback loop in the &Sgr;-&Dgr; converter of
FIG. 1
keeps the average of the digital output Y equal to the average of the analog input X. This is accomplished by integrating the difference between X and the analog equivalent of Y in integrator
2
, and by integrating the difference between the output of integrator
2
and the analog equivalent of Y in integrator
4
. As is known in the art, the quantization error of the coarse ADC is pushed out to frequencies out of the signal bandwidth and can be digitally filtered out. This results in a high resolution ADC, even though the coarse ADC embedded in the loop has low resolution.
In conventional digital domain shuffling schemes for the &Sgr;-&Dgr; type of converter the shuffling network takes the digital output of the coarse quantizer (ADC), shuffles it, and then sends the shuffled digital code to the DAC. In a pipelined ADC, the coarse quantizer is also typically a flash ADC. In pipelined ADCs the shuffling network takes the output of the latches in the flash ADC as its inputs. Examples of such digital domain shuffling schemes can be found in L. R. Carley, “Noise Shaping Coder Typology for 15-bit Converters,”
IEEE J. Solid
-
State Circuits,
S.C. 24 No. 2, pp. 267-273, April 1989; B. H. Leung and S. Sutarja, “Multibit &Sgr;-&Dgr; A/D Converter Incorporating a Novel Class of Dynamic Element Matching Techniques,”
IEEE Trans. Circuits and Syst. II,
Vol. 39, No. 1, pp. 35-51, January 1992; F. Chen and B. Leung, “A High Resolution Multipbit Sigma-Delta Modulator with Individual Level Averaging,”
IEEE J. Solid
-
Stagte Circuits,
vol. 30, pp. 453-460, April 1995; R. T. Baird and T. Fiez, “Improved &Sgr;-&Dgr; DAC Linearity Using Data Weighted Averaging,” Proc. 1995
IEEE Int. Symp. Circuits Sys.,
Vol. 1, pp. 13-16, May 1995; R. Adams and T. Kuan, “Data-Directed Scrambler for Multi-Bit Noise Shaping D/A Converters,” U.S. Pat. No. 5,404,142, Assigned to Analog Devices, Inc., Apr. 4, 1995; and “W. Williams III, “An Audio DAC with 90 dB Linearity using MOS to Metal-Metal is Charge Transfer,”
ISSCC Dig. Tech. Papers,
pp. 58-59, San Francisco, 1998.
In both types of ADC, the shuffling schemes are implemented in the digital domain, after the latch in the flash ADC, limiting the overall speed of the ADC. It is, therefore, desired to have an ADC having shuffling, but with less speed degradation from such shuffling than is the case in the prior art.
SUMMARY OF THE INVENTION
The present invention provides a method for use in a system including an analog-to-digital converter subsystem (ADC) and a digital-to-analog converter subsystem (DAC), wherein the ADC samples an input signal at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input signal. The method is applicable to such systems in which the DAC includes a plurality of elements, such as capacitors or current sources, each connectable in a plurality of different ways in accordance with the digital outputs so as to contribute a portion of an analog output signal corresponding to the digital output, the magnitude of the portion being determined by a way the element is connected. The method is one for shuffling the elements, and includes the following steps. A plurality of coded analog signals are generated based on the input voltage, each such coded analog signal being above or below a predetermined threshold so as to correspond to a way one of the elements is connected. A predetermined sequence of control codes is provided. The coded analog signals are shuffled in accordance with the sequence of control codes. The shuffled coded analog signals are latched as digital values, and the plurality of elements are connected in ways determined in accordance with the shuffled codes.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.
REFERENCES:
patent: 5257026 (1993-10-01), Thompson et al.
patent: 5404142 (1995-04-01), Adams et al.
patent: 5598472 (1997-01-01), Schuchman et al.
patent: 6218977 (2001-04-01), Friend et al.
patent: 6304608 (2001-10-01), Chen et al.
Rex T. Baird, et al., “Improved &Dgr;&Sgr; DAC Linearity Using Data Weighted Averaging” IEEE, pp. 13-16, 1995.
Feng Chen, et al., “A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging” IEEE Journal of Solid-State Circuits, vol. 30, No. 4, pp. 453-460, Apr. 1995.
Bosco H. Leung, et al., “Multibit &Sgr;-&Dgr; A/D Converter Incorporating a Novel Class of Dynamic Element Matching Techniques” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, No. 1, pp. 35-51, Jan. 1992.
L. Richard Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters” IEEE Journal of Solid-State Circuits, vol. 24, No. 2, pp. 267-273, Apr. 1989.
Louis A. Williams, III, “An Audio DAC with 90dB Linearity Using MOS to Metal-Metal Charge Transfer” Texas Instruments.
Brady III W. James
Jean-Pierre Peguy
Lauture Joseph J
Moore J. Dennis
Telecky , Jr. Frederick J.
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