High speed address transition detector circuit for dynamic read/

Details High speed address transition detector circuit for dynamic read/ High speed address transition detector circuit for dynamic read/

1984-07-09

1986-12-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307262, 307269, 307480, 365230, H03K 5153, G11C 800

Patent

active

046331026

ABSTRACT:
A transition of an address input of a memory device is detected in a CMOS circuit having a pair of AND gates Or'ed together. One AND gate receives the input bit and a delayed complement of this bit. The other AND gate receives the complement of the input bit and a delayed version of the true bit. The delays are RC circuits with time constants longer than the transition times. The output of the gates uses a pull-up device to restore a zero level after each transition is indicated. A number of these transition detectors may be OR'ed together to monitor all of the address bits of a memory device.

REFERENCES:
patent: 4286174 (1981-08-01), Dingwall

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