High speed adder design for a multiply-add based floating...

Details High speed adder design for a multiply-add based floating... High speed adder design for a multiply-add based floating...

2003-12-11

2009-02-10

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S501000

Reexamination Certificate

active

07490119

ABSTRACT:
An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.

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Goldberg, David; “What Every Computer Scientist Should Know About Floating-Point Arithmetic”; Computing Surveys, Mar. 1991; Association for Computing Machinery, Inc.
Ferguson, M. I. et al; “A Multiplier with Redundant Operands”; 33rdAnnual Conference on Signals, Systems, and Computers; Asilomar, Pacific Grove, California; Oct. 1999.

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