High speed adder

Details High speed adder High speed adder

2007-10-02

2007-10-02

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10695489

ABSTRACT:
Provided is an adder composed of (N+1) circuit stages in the ease of 2.sup.N bits. In the case of N=4 (that is, 16 bits), provisional carries that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are generated by conditional cells in a first circuit stage. In second to fourth circuit stages, the provisional carries corresponding to higher seven bits other than the most significant bit are converted into provisional sums by converters in a circuit stage in which the provisional carries are transferred. In addition, actual carry signals are selected from the provisional carries corresponding to lower seven bits other than the least significant bit in a circuit stage in which the provisional carries are transferred. In a fifth circuit stage, bit sums for each of the bits are generated and outputted.

REFERENCES:
patent: 5257218 (1993-10-01), Poon
patent: 5285406 (1994-02-01), Lynch et al.
patent: 5631860 (1997-05-01), Morinaka
patent: 6134576 (2000-10-01), Hossain et al.
Kuo-Hsing Cheng, et al. The Improvement of Conditional Sum Adder for Low Power Applications/ 1998 IEEE pp. 131-134.

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