High speed adder

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G06F 750

Patent

active

048978094

ABSTRACT:
An improved cascadable adder (11) which, through the use of merged logic, provides high speed operation in the presence of input loading and internal fan-out limitations. The invention may be implemented in gallium arsenide technology and includes a first circuit (13) for exclusive ORing first bits (A.sub.1, B.sub.1) of first and second digital words (A, B) respectively; and a second circuit (37) operatively connected to the first circuit (13) for generating, with only two gate delays, a carry (C.sub.1) associated with the summing of the first bits.

REFERENCES:
patent: 4464728 (1984-08-01), Nash
patent: 4623982 (1986-11-01), Ware
patent: 4733365 (1988-03-01), Nagamatsu
patent: 4761760 (1988-08-01), Tomoji

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