High-speed adder

Details High-speed adder High-speed adder

1975-06-18

1976-07-20

Dildine, Jr., R. Stephen

Registers

Transfer mechanism

Traveling pawl

G06F 750

Patent

active

039708330

ABSTRACT:
A high-speed adder circuit capable of performing addition with binary nums in 1's complement, 2's complement or sign-magnitude formats. The adder can be made in the form of a single chip that can be assembled in multiple units to expand its capacity. There is a provision for converting minus zero to plus zero so as to prevent oscillations from occurring in the loop circuit. Also, the sum output is automatically shifted to the correct format when an overflow condition occurs.

REFERENCES:
patent: 3863061 (1975-01-01), Kazantzis

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