High-speed, adaptive IDDQ measurement

Details High-speed, adaptive IDDQ measurement High-speed, adaptive IDDQ measurement

2000-04-13

2002-01-29

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S537000

Reexamination Certificate

active

06342790

ABSTRACT:

TECHNICAL FIELD
This invention facilitates very fast power supply quiescent current (IDDQ) measurements, and provides a technique for performing signature analysis on the measurements, in order to screen defective devices in the presence of high background leakage currents.
BACKGROUND
Integrated circuits containing very large numbers of devices such as transistors must be tested for defects before they are shipped to customers. A technique called “IDDQ testing” is commonly used in defect testing of integrated circuits containing CMOS devices. IDDQ testing is performed by stopping all clock signals applied to the device under test (DUT). This places the DUT in a quiescent state in which the current flow through the DUT is characterized by a so-called “IDDQ” quiescent current in contrast to the “IDDD” dynamic current which flows during normal clocked operation of the DUT. Various defects can be detected by measuring IDDQ current flow through the DUT when the DUT is in the quiescent state, and comparing the measured IDDQ value to predefined values representative of IDDQ current values for similar devices which are known to be either defective or defect-free.
Conventional IDDQ testing becomes impractical as the fundamental dimensions of the DUT are reduced, since the background leakage current increases as such dimensions are decreased. It is necessary to reduce such dimensions in order to increase the number of devices that can be contained in an integrated circuit. But, the saturation current of a single defective transistor stays about the same, or may even decrease. Consequently, a change in IDDQ current due to the presence or absence of a defect becomes much smaller than changes caused by inherent process variations from one device to another, or changes due to temperature variations, making it impossible to distinguish good devices from bad devices with a fixed measurement limit.
Typically, IDDQ testing is performed by automated test equipment (ATE) which places the DUT in the quiescent state by applying a test pattern electronic signal to the DUT. A parametric measurement unit (PMU) or high precision ammeter is then used to measure the IDDQ current flowing through the DUT. This is an extremely slow technique, in that only a small number of measurements (about
10
) can be included in a production test. The partitioned design methodology typically used for “system-on-a-chip” (SOC) devices severely limits the maximum test coverage which can be obtained if only a small number of IDDQ measurements can be made.
Alternate, higher-speed IDDQ measurement techniques have been based on loadboard-mounted IDDQ monitoring circuitry. In one such technique (see M. Keating and D. Meyer, “A New Approach to Dynamic IDD Testing,”
Proceedings of IEEE International Test Conference
, 1987, pp. 316-321) the decay of the DUT decoupling capacitance is monitored after the DUT is disconnected from the device power supply (DPS). This technique can be enhanced by differentiating the decay signal and comparing the result to a fixed reference (see: K. M. Wallquist, Achieving IDDQ/ISSQ Production Testing With QuiC-Mon,
IEEE Design & Test of Computers
, Vol 12, Fall 1995). But, both techniques suffer from the disadvantage that they are sensitive to the device decoupling capacitance, and also that they require disconnecting the DUT from the DPS during operation, which can lead to latch-up conditions.
More recently, “delta IDDQ testing” has been used in IDDQ testing of sub-micron devices (see U.S. Pat. No. 5,889,408). However, delta IDDQ testing has limited viability, since background leakage current values can exceed IDDQ values on some defect-free sub-micron devices. The problem is especially acute for very deep sub-micron devices having fundamental dimensions less than 0.25 &mgr;m. Any methodology based on an ability to discriminate between fixed IDDQ values and fixed background leakage current values can be expected either to falsely fail defect-free devices, or falsely pass defective devices at some point as fundamental DUT dimensions decrease and background leakage currents increase.
What is required is an IDDQ testing technique that is fast enough to permit good IDDQ test coverage to be obtained on SOC-type devices, without compromising production test times. Preferably, at least one IDDQ measurement should be made during execution of the scan vectors for each partition in the DUT, while maintaining a total test time of under one second (including vector execution). This requires a maximum test time on the order of a few milliseconds. The technique must be insensitive to loadboard construction to ensure reliable correlation between multiple test fixtures and ATE platforms; must not subject the DUT to possible damage due to latch-up; and, must be insensitive to anticipated variations in background leakage current due to normal process and temperature variations encountered in fabrication of deep sub-micron devices (i.e. devices having fundamental dimensions less than 0.25 &mgr;m). The present invention satisfies these considerations.
SUMMARY OF THE INVENTION
The invention facilitates measurement of IDDQ values which characterize a DUT. A current mirror “mirrors” the current flowing from a power supply through the DUT, such that the same current flows through a second current path coupling the power supply to an integrator. A first switch switches the second current path between a first state in which current flowing in the second current path bypasses the integrator, and a second state in which current flowing in the second current path flows through the integrator. The rise time of the voltage produced across the integrator as current flows through the integrator is proportional to and therefore representative of an IDDQ value which characterizes the DUT.
Preferably, the integrator is a capacitor and the first switch is a transistor connected across the capacitor. Application of a first logic signal to the transistor turns the transistor on, causing current flowing in the second current path to bypass the capacitor, thereby discharging the capacitor. Application of a second logic signal to the transistor turns the transistor off, causing current flowing in the second current path to flow through the capacitor, thereby charging the capacitor. The rise time of the voltage produced across the charging capacitor is proportional to and therefore representative of an IDDQ current value which characterizes the DUT.
A buffer connected in parallel across the capacitor provides a means for measuring rise time of the voltage produced across the capacitor during charging of the capacitor. An optional second switch can be coupled between the power supply, current mirror and DUT to disconnect the DUT from the current mirror, without disconnecting the DUT from the power supply. This facilitates bypassing of the current mirror during high-current functional tests such as at-speed tests, without subjecting the DUT to possible damage due to latch-up which can occur if the DUT is disconnected from the power supply. Advantageously, the second switch may be a double pole double throw relay switch having a first pole pair switchable between the power supply and the current mirror and a second pole pair switchable between the current mirror and a null point.
In some embodiments, the capacitor need not be a discrete capacitor component, but may be represented by the transistor's inherent discharge (parasitic drain-to-source) capacitance C
DS
, if C
DS
has the appropriate order of magnitude.
The invention also provides a method of measuring IDDQ values characterizing a DUT. Current flowing through the DUT is “mirrored” to flow through a second current path. The DUT is first operated in a non-quiescent state while the second current path is switched to cause the mirrored current path to bypass a capacitor, thereby discharging the capacitor. During operation of the DUT in the non-quiescent state, test vectors are applied to the DUT until the DUT enters the quiescent state. The DUT is maintained in the quiescent state w

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