High slew rate input differential pair with common mode...

Details High slew rate input differential pair with common mode... High slew rate input differential pair with common mode...

1999-05-25

2001-06-19

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S563000

Reexamination Certificate

active

06249153

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to differential pairs and, in particular, the present invention relates to a differential pair capable of attaining a high slew rate and a common mode input to ground.
2. Background of the Invention
Differential pairs are widely used in constructing analog circuits such as operational amplifiers and comparators. A conventional emitter-coupled
FIG. 1
a
, NPN transistors
12
a
and
14
a
form the emitter-coupled differential pair driven by constant current source
10
a
, which provides a constant current I
T
, also called the tail current, to the differential pair. In
FIG. 1
a
, a differential voltage V
d
represents the difference between the input voltages applied to the base terminals of transistors
12
a
and
14
a
. Collector currents I
1
and I
2
change in response to the differential voltage V
d
. However, the sum of collector currents I
1
and I
2
always equals I
T
. When transistors
12
a
and
14
a
are matched, collector currents I
1
and I
2
are the same and equal (½I
T
) when V
d
is zero, i.e., when input voltages at the base terminals of transistors
12
a
and
14
a
are the same. When a differential voltage is applied to V
d
, currents I
1
and I
2
will either increase or decrease depending on the polarity of voltage V
d
. Referring to
FIG. 1
a
, if a positive V
d
is applied, the collector currents I
1
and I
2
will become:
I
1
=½I
T
+&Dgr;I, and
I
2
=½I
T
−&Dgr;I,
where &Dgr;I is the change in collector current due to V
d
. A differential output current and a differential output voltage develop at the collector terminals of transistors
12
a
and
14
a.
A differential pair can also be constructed using MOS transistors as shown in FIG
1
b
. NMOS transistors
12
b
and
14
b
form a differential pair biased by current source
10
b
. One skilled in the art will appreciate that the operation of the MOS differential pair in
FIG. 1
b
is analogous to the bipolar differential pair in
FIG. 1
a
. One skilled in the art will also appreciate that PNP transistors or PMOS transistors can be used to form the differential pair as shown in
FIGS. 2
a
and
2
b
respectively.
The conventional differential pairs illustrated in
FIGS. 1
a-b
and
2
a-b
have several disadvantages. One disadvantage of the conventional differential pair is that in order to increase the gain of the differential pair, the tail current I
T
needs to be increased. In the differential pairs illustrated above, the gain is maximized when &Dgr;I, the change in collector current in response to the differential input voltage V
d
, is maximized. The change in current &Dgr;I is a function of the transconductance (g
m
) of the transistors and is defined by the equation:
&Dgr;I=g
m
V
d
.
The transconductance g
m
of a transistor is a function of the DC collector or source current and the threshold voltage of the transistor. The transconductance g
m
of the bipolar differential pair is given by:
g
m
=
1
2
⁢
I
T
V
T
where V
T
is the threshold voltage of the bipolar transistor. Similarly, the transconductance of the MOS differential pair is given by:
g
m
=
2
⁢
K
⁡
(
I
T
2
)
where K is a parameter relating to the device characteristics of the MOS transistor. In order to increase the gain of the conventional differential pair (that is, to maximize &Dgr;I), the transconductance g
m
of equations for g
m
provided above, increasing g
m
requires increasing the tail current I
T
. However, it is undesirable to increase the tail current I
T
because a large I
T
causes an increase in the quiescent current of the circuit, resulting in increased heat and power consumption.
Another disadvantage of the conventional differential pair is that the common mode input voltage V
cm
cannot be brought to ground while still maintaining operation of the differential pair. The common mode input voltage V
cm
is a voltage added to the differential input voltage V
d
before the input voltages are applied to the input terminals of the differential pair. Defining V
1
as the input voltage applied to the gate or base of one of the transistors of the differential pair, and V
2
as the input voltage applied to the base or gate of the other transistor in the differential pair, the differential input voltage V
d
and the common mode input voltage V
cm
are defined as:
V
cm
=
V
1
+
V
2
2
.
Following the above equations, the input voltages V
1
and V
2
are given by:
V
1
=
V
cm
+
V
d
2
,
and
V
2
=
V
cm
-
V
d
2
.
Using the NPN differential pair of
FIG. 1
a
as an example, voltage V
cm
cannot be brought to ground by setting voltages V1 and V2 to zero volt because a minimum voltage of (V
BE
+V
CE(sat)
) must be kept at the emitter terminals of transistors
12
a
and
14
a
in order to keep current source I
T
on. The situation is the same for the PNP differential pair shown in
FIG. 2
a
. Since the collector terminals of transistors
22
a
and
22
b
are typically connected to a current mirror acting as an active load for the output of the differential pair. The common mode voltage V
cm
cannot be brought to ground because the current mirror will be shut off.
The conventional differential pair has yet another disadvantage of a limited slew rate due to the tail current I
T
. This is described with reference to
FIG. 3
, which is a circuit schematic of a conventional bipolar differential amplifier. Differential amplifier
300
includes an emitter-coupled differential pair (NPN transistors N
1
and N
2
) coupled to a current mirror (transistors P
1
and P
2
) as the active load. A differential voltage V
d
is applied to the base terminals (nodes
314
and
316
) of transistors N
1
and N
2
. Constant current source
312
, connected to the emitter terminals of transistors N
1
and N
2
(node
308
), provides a constant tail current I
T
to the differential pair. The output terminal of the differential pair (node
318
) is connected to an integrating stage including an amplifier
302
and a compensation capacitor
304
. Amplifier
302
and compensation capacitor
304
are connected in parallel between node
318
and node
320
. Node
320
is the output voltage Vout of different amplifier
300
.
One important performance parameter of a differential amplifier is the slew rate which measures how closely the output voltage Vout tracks changes in the input differential voltage V
d
. Slew rate is defined as the rate of change of the output voltage Vout before Vout reaches its final value. The slew rate is limited by the amount of current available at the output of the differential pair (node
318
) to charge compensation capacitor
304
when a large differential input voltage is applied. Thus, the maximum slew rate attainable for differential amplifier
300
is limited by the maximum current that the different pair (transistors N
1
and N
2
) can deliver at output node
318
to charge capacitor
304
. For differential amplifier
300
, the maximum current is the maximum collector current of transistor N
2
, which is the tail current I
T
Therefore, the maximum slew rate for differential amplifier
300
is provided by:
Slew
⁢
 
⁢
Rate
=
ⅆ
V
out
ⅆ
t
&RightBracketingBar;
max
=
I
T
C
c
where Cc is the capacitance of compensation capacitor
304
. In order to attain a very high slew rate, either the tail current I
T
needs to be increased or the capacitance Cc of capacitor
304
needs to be decreased. However, it is undesirable to decrease the compensation capacitance Cc because circuit stability will be compromised. Therefore, the tail current I
T
has to be increased to attain a high slew rate. As described above, increasing I
T
is not desirable because it leads to an increase in quiescent current in the circuit.
FIG. 4
is a circuit diagram of a differential amplifier
400
constructed of an NMOS differential pair and a PMOS current mirror. One skilled in the art will appreciate that the operation of differential amplifier
400
is analogous to differential amplifier
300
in

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