High slew rate differential amplifier circuit

Details High slew rate differential amplifier circuit High slew rate differential amplifier circuit

2000-09-15

2002-05-21

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S255000, C330S257000

Reexamination Certificate

active

06392485

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a differential amplifier circuit, and in particular, to a high slew rate differential amplifier circuit for use in a driver for a liquid crystal display device.
BACKGROUND OF THE INVENTION
A conventional rail-to-rail differential amplifier circuit is configured as shown in FIG.
3
.
A main section of the circuit comprises a P-type MOS differential input section
1
composed of transistors M
1
, M
2
, and M
3
, N-type MOS differential input section
2
composed of transistors M
4
, M
5
, and M
6
, a current mirror circuit
3
composed of transistors M
7
, M
8
, M
9
, and M
10
, a current mirror circuit
4
composed of transistors M
11
, M
12
, M
13
, and M
14
, and a push pull output tier
5
composed of transistors M
15
and M
16
, wherein reference Vdd denotes a positive power voltage and reference Vss denotes a negative power voltage.
A non-inverted input (+) is connected to gates of the transistors M
3
and M
5
, while an inverted input (−) is connected to gates of the transistors M
2
and M
4
. An output of the P-type MOS differential input section
1
from the transistors M
2
and M
3
is input to the current mirror circuit
4
, while an output of the N-type MOS differential input section
2
from the transistors M
4
and M
5
is input to the current mirror circuit
3
. The current mirror circuits
3
and
4
are connected together via resistors R
1
and R
2
, a gate of a transistor M
15
of the push pull output tier
5
is connected to a connection between the transistor M
10
and one end of the resistor R
2
, while a gate of a transistor M
16
of the push pull output tier
5
is connected to a connection between the transistor M
12
and the other end of the resistor R
2
. Alternatively, the resistors R
1
and R
2
can be configured using MOS transistors.
References C
1
and C
2
denote phase compensating capacities, and references Vb
1
to Vb
4
denote bias voltages set to allow the corresponding transistors to operate appropriately. An external load CL is connected between the output of the push pull output tier
5
and the negative power voltage Vss.
A current flowing through the transistor M
1
acting as a constant current source for the P-type MOS differential input section
1
is defined as Im
1
, whereas a current flowing through the transistor M
6
acting as a constant current source for the N-type MOS differential input section
2
is defined as Im
6
. When a non-inverted input voltage (Vin+) and an inverted input voltage (Vin−) are equal, that is, in a steady state, currents flowing through the transistors M
2
and M
3
of the P-type MOS differential input section
1
are each (Im
1
)·(1/2), whereas currents flowing through the transistors M
4
and M
5
of the N-type MOS differential input section
2
are each (Im
6
)·(1/2).
When the steady state changes to a state where the non-inverted input (Vin+) is higher than the inverted input voltage (Vin−), most of the constant current (Im
1
) on the P-type MOS input side flows through the transistor M
2
to increase a current flowing through the transistor M
13
. Thus, the current mirror circuit
4
increases currents flowing through the transistors M
12
and M
14
to reduce a gate voltage of the output transistor M
16
to diminish a current flowing through the output transistor M
16
as well as a lead-in current to an external load CL. A gate voltage of the output transistor M
15
also decreases to increase a current flowing through the M
15
to charge the external load CL. At this point, most of the constant current (Im
6
) on the N-type MOS input side flows through the transistor M
5
to reduce a current flowing through the transistor M
10
to lessen a gate voltage of the output transistor M
15
. Accordingly, the current flowing through the M
15
increases to charge the external load CL to raise an output voltage Vout.
When the steady state changes to a state where the non-inverted input (Vin+) is lower than the inverted input voltage (Vin−), most of the constant current (Im
1
) on the P-type MOS input side flows through the transistor M
3
to reduce the current flowing through the transistor M
12
. Thus, the gate voltage of the output transistor M
16
rises to increase the current flowing through the output transistor M
16
as well as the lead-in current to the external load CL.
At this point, most of the constant current (Im
6
) on the N-type MOS input side flows through the transistor M
4
to increase a current flowing through the transistor M
7
. Thus, the current mirror circuit
3
increases currents flowing through the transistors M
8
and M
10
to raise a gate voltage of the output transistor M
15
to diminish the current flowing through the output transistor M
15
as well as a speed at which the external load CL is charged. Accordingly, the gate voltage of the output transistor M
16
rises to increase the current flowing through the M
16
as well as the lead-in current to the external load CL to lower the output voltage Vout.
DISCLOSURE OF THE INVENTION
Recent liquid crystal display devices for use in TVs or personal computer displays comprise larger screens with a higher resolution. Source drives are correspondingly required to have the capability of driving a larger load at a higher speed.
FIG. 6
schematically shows a liquid crystal display device.
A liquid crystal panel
10
comprises an active matrix liquid panel having a pixel
13
located at an intersection between each scanning line
11
and a corresponding data line
12
and a drive device for driving the liquid crystal panel. The drive device
14
comprises source drivers
16
controlled by a controller
15
and gate drivers
17
.
The source driver
16
receives a signal from the controller
15
to drive the pixel
13
, and the gate driver
17
switches a gate of a TFT (a thin film transistor)
18
.
For example, an XGA (1,024×768) liquid crystal panel requires 1024×3 (R, G, B)=3,072 outputs, so that if the source driver has 384 outputs, 3,072/384=8 source driver chips are used.
One source driver chip with the 384 outputs has 384 differential amplifier circuits mounted thereon.
To accommodate a high-resolution liquid crystal panel with a UXGA (1,600×1,200) or a QXGA (2,048×1,536), a source driver with 480 or 516 outputs is required and in this case, one source driver
16
chip has 480 or 516 differential amplifier circuits mounted thereon.
Due to the larger screen and higher resolution of the liquid crystal panel
10
, the source driver
16
is required to have the capability of driving a larger load at a higher speed while maintaining power consumption at a low level. Thus, the differential amplifier circuit mounted on the source driver
16
must be able to maintain current consumption at a low level and have a higher slew rate.
Furthermore, since the source driver
16
has a large number of differential amplifier circuits mounted thereon as described above, the slew rate must be improved by adding simple circuits having as small circuit area as possible so as not increase the chip area.
Since the source driver requires a large dynamic range, it often employs rail-to-rail amplifiers such as conventional differential amplifier circuits. The slew rate of such differential amplifier circuits for driving an external load is in proportion to a current value of a differential input section and is in inverse proportion to a capacity value of a phase compensating capacity. To improve the slew rate without adding slew rate improving circuits so as not to increase the circuit area, the currents Im
1
and Im
6
through the constant current source transistors M
1
and M
6
of the differential input section may be increased or phase compensating capacities C
1
and C
2
may be diminished.
A problem is, however, that an increase in the current through the differential input section increases the steady-state current and thus current consumption, while reduction of the phase compensating capacity degrades stability.
It is an

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