Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-12-21
2004-03-09
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S537000, C330S303000, C330S305000, C330S306000, C330S284000
Reexamination Certificate
active
06703682
ABSTRACT:
BACKGROUND
The present invention relates generally to semiconductor devices, and more particularly, to a method and apparatus for providing high sheet resistance in a circuit design using conventional CMOS components.
There are applications in analog integrated circuits which require high resistances, such as an integrated light to voltage converter. A light to voltage converter can be implemented by connecting a photodiode to the summing junction of an operational amplifier with a resistor in the feedback loop. To generate a usable signal with the very small current generated by the photodiode requires a large feedback resistor.
In integrated circuits, resistors are usually constructed using the same layers that are used for the fabrication of the active devices (e.g., transistors) in the circuit. In CMOS circuitry, the layers commonly used for resistors are polysilicon (e.g., used for the gates of MOS devices), diffusion (e.g., used for the source/drain of MOS devices) or N-well (e.g., used to isolate PMOS devices from the P− substrate).
Resistors have conventionally been implemented by defining a geometry (e.g., a rectangle or serpentine structure) in a resistive layer and contacting the two ends of the particular geometry. The value of the resistor is given by the expression:
Resistance=(length/width)*sheet resistance
From the above expression, it follows that the area of a resistor is proportional to its value and inversely proportional the sheet resistance of the resistive material. However, it should be noted that the geometry is limited by the manufacturing process to minimum widths. Accordingly, the width cannot be made arbitrarily small in order to achieve a high resistance. Also, resistors with a minimum width dimension have greater resistance variation due to the manufacturing process width variations. Furthermore, all integrated circuit (IC) resistors have a high frequency loss caused by parasitic capacitance that increases as the length squared of the resistor.
Sheet resistances found in low cost CMOS manufacturing processes are relatively low, which implies that a large value resistor will require a large area. As an example, a one (1) megohm resistor implemented in a one (1) micron CMOS manufacturing process with 50 ohm per square polysilicon will occupy approximately 100,000 square microns. With such a 1 micron CMOS manufacturing process, resistances in the tens of megohms are impractical, or at best, costly.
Accordingly, high sheet resistances in integrated circuits have conventionally entailed additional processing steps. In standard silicon processing, high sheet resistance can usually be achieved by selective doping of polysilicon layers or by the deposition of thin film resistors such as SiCr. Even with these added processing steps, practical sheet resistances for analog circuits are typically limited to 500-2000 ohms per square.
In addition to the above, it is possible to use a MOS transistor operating in the so called “linear” region as a resistor. A technique for using MOS devices in this manner with tightly controlled tolerances was disclosed by Yannis Tsividis in 1982 when he reported on a filter circuit using this technique at the International Solid State Circuits Conference. While this technique achieved relatively high values of resistance, the technique required fully differential circuitry and, furthermore, was not capable of operation at the negative rail. Since that time, a great deal of work has been reported in the literature on MOS resistors in differential circuitry applications.
A method of using PMOS resistors in a single ended (as opposed to a differential configuration) is described in Tsividis,
Six
-
Terminal MOSFET's: Modeling and Applications in Highly Linear, Electronically Tunable Resistors
, the Journal of Solid State Circuits, January, 1997. Referring now to
FIG. 1
, a single ended PMOS resistor
10
is shown. For the PMOS resistor, connections are made to the source
12
and drain
14
, the source and drain ends of the gate (
16
,
18
), and the source and drain ends of the N-well (
20
,
22
). The six terminal MOS device can be considered as a infinite number of infinitesimally short devices in series.
In one example, the drain to source voltage (Vds) is sampled and fed back via auxiliary circuitry (not shown) to the gate and well terminals so that the distributed gate and well voltages track the drain to source voltage. In other words, the voltage from nodes Gd to Gs and from Wd to Ws are controlled to be the same as from D to S. In addition, the voltage from node Gs to node S is high enough that the devices operate in the linear region. Equations describing these conditions are:
V
(
Gs
)=
V
(
S
)+tuning voltage (1)
V
(
Gd
)=
V
(
Gs
)+
V
(
D
)−
V
(
S
) (2)
V
(
Ws
)=
V
(
S
) (3)
V
(
Wd
)=
V
(
D
) (4)
With respect to the above, the well terminals are not connected to the source and drain terminals directly, but are driven by amplifiers (not shown) buffering the source and drain voltages.
In the configuration of
FIG. 1
, the gate to source voltage and the source to bulk voltage for each infinitesimal device increases exactly as the drain to source voltage. From classical MOS current equations, it is easily shown that the resistance of the individual elements, and hence the resistance of the entire distributed device, remains constant with increasing Vds.
It is noted that the 6-terminal MOS technique described above can be used to obtain highly linear resistances with high sheet values. However, the configuration is not suitable for implementing resistors in a conventional N-well process when either drain or source must operate at or near the negative rail of the circuit since the voltage at the corresponding gate would have to be below the rail. (The opposite argument holds in a P-well process.) For the configuration of
FIG. 1
to work at or near the rail, it would require depletion mode devices. However, depletion mode devices are not available in a standard CMOS process. Accordingly, the 6-terminal MOS resistor is not suitable for single-ended, ground referenced applications.
Turning now to
FIGS. 2 and 3
, a diode
26
for use in a light to voltage converter
24
implemented in a NMOS process is shown. The light to voltage converter
24
uses an N-well to P− epi/P+ substrate diode
26
for the photodiode. To minimize thermal leakage currents, it is desirable to operate the photodiode
26
of
FIG. 2
at zero bias. This is accomplished by connecting the cathode of the diode
26
to the summing junction of an op amp
28
which has the non-inverting input connected to the substrate, such as shown in FIG.
3
. Note that the summing junction of the op amp operates at the same potential as the substrate. Accordingly, a 6 terminal PMOS device cannot be used as a feedback resistor
30
for the application of FIG.
3
.
A method and apparatus is thus needed for providing highly linear resistance with high sheet values, and for implementing resistors in a conventional CMOS process when either drain or source must operate at or near the rail of a circuit.
SUMMARY
A method and apparatus is disclosed for providing highly linear resistance with high sheet values, and for implementing resistors in a conventional CMOS process when either drain or source must operate at or near the rail of a circuit.
According to one embodiment of the present invention, a five terminal MOS resistive device includes a drain terminal, a source terminal, a singular bulk terminal, a first gate terminal, and a second gate terminal. The first gate terminal is adjacent to the source terminal of the device, and the second gate terminal is adjacent to the drain terminal of the device. Further, the gate terminal is composed of a resistive material so that when a voltage is applied to the first and second gate terminals, a voltage drop across the gate terminal is equally distributed along the length of an electrical channel of the MOS resistive de
Eckert George
Haynes and Boone LLP
Nguyen Joseph
Texas Advanced Optoelectronic Solutions, Inc.
LandOfFree
High sheet MOS resistor method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High sheet MOS resistor method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High sheet MOS resistor method and apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3192314