High-sensitivity differential data latch system

Details High-sensitivity differential data latch system High-sensitivity differential data latch system

2005-03-01

2005-03-01

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S218000

Reexamination Certificate

active

06861888

ABSTRACT:
A data latch system includes a data input for providing a first data bit having a first duration and a second data bit having a second duration, and a data output for providing the first data bit for the first and second durations. First sampling circuitry is connected to the data input and the data output for the first duration to provide the first data bit to the data output. Second sampling circuitry is connected to the data input and the data output for the second duration to provide the second data bit inverted to the data output. Holding circuitry connected to the data output for the second duration holds the first data bit and the second sampling circuitry connects the second data bit inverted to the data output to enhance the held first data bit when the first and second data bits have different states.

REFERENCES:
patent: 5510734 (1996-04-01), Sone
patent: 5850155 (1998-12-01), Matsumoto
patent: 6798263 (2004-09-01), Leon
patent: 20030141912 (2003-07-01), Sudjian

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