Data processing: measuring – calibrating – or testing – Measurement system – Measured signal processing
Reexamination Certificate
2002-09-16
2004-06-22
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Measured signal processing
Reexamination Certificate
active
06754613
ABSTRACT:
TECHNICAL FIELD
This invention relates to time-to-digital conversion (“TDC”), more specifically to time to digital conversion methods and apparatus which use a differential period between frequency-mismatched oscillators to measure time between events to high resolution. The invention has particular application in measuring jitter characteristics in high frequency digital signals. Specific embodiments of the invention are useful for on-board or on-chip self testing of timing circuits such as phase-locked loops (“PLLs”), delay-locked loops (“DLLs”), and serialiser/deserializers. Another aspect of the invention relates to a finely tunable digital ring oscillator suitable for use in TDC systems according to the invention.
BACKGROUND OF THE INVENTION
The timing of signals in high speed digital systems can be important to the proper operation of such systems. There is a need for ways to measure time characteristics of digital signals. Jitter is an example of such a time characteristic. Jitter is an important characteristic of high-speed digital signals generally. While there exist sophisticated stand-alone devices capable of measuring jitter in high-speed digital signals, such devices tend to be extremely complicated and expensive. Jitter testing typically requires a long test time. Further, where the signal to be tested is internal to an integrated circuit, it may not be practical to use a stand-alone device to test for jitter.
Timing circuits such as phase-locked loops, delay-locked loops, and serializers/deserializers are used widely in many high-speed integrated circuits. These circuits are used in many applications. Some examples are synthesizing clock signals, recovering data, realigning clock edges and timing the transmission of data.
Jitter in the outputs of such timing circuits can is cause malfunctions. These malfunctions can be very difficult to diagnose. As complex-System on Chip (“SOC”) integrated circuits become even more complicated and clock speeds increase into the gigahertz range, it becomes increasingly costly and time consuming to test such circuits.
The definition of jitter varies depending on the field of application. In sequential circuits, e.g. CPUs, jitter is defined as the variation of the clock period, known as “cycle-to-cycle” or “period jitter”. As shown in
FIG. 1A
, period jitter samples are collected by measuring the duration of each period of the signal IN
1
.
For both period and accumulative jitter measurements, M jitter samples are collected to calculate jitter characteristics, such as rms, peak-to-peak, or frequency components. For example, the rms jitter may be obtained by performing the following computations:
T
J
(
rms
)
=
1
M
∑
i
=
0
M
-
1
(
T
J
(
i
)
-
T
_
)
2
(
1
)
where
T
_
=
1
M
∑
i
=
0
M
-
1
T
J
(
i
)
is the estimate of average signal period.
Some jitter specifications for PLLs used in digital communication interfaces are intrinsic jitter, jitter tolerance and jitter transfer. These specifications are given in standards for each application (e.g., see Bell Research Laboratories SONET transport systems:
Common criteria network element architectural features
GR-253 core, Issue 1, pp. 5-81, December, 1994 for SONET interfaces).
In serial communication applications, jitter can be defined as the short-term variations of a digital signal's significant instants, e.g. rising edges, from their ideal position in time. Such jitter is often denoted as “accumulative jitter” and is described as a phase modulation of a clock signal. In a clock synthesis circuit, where the absolute jitter is important, often a jitter-free (practically low-jitter) reference signal is used for jitter measurement. In such a case, the difference between the position of corresponding edges of the signal (IN
1
) relative to the reference clock (REF) indicates the jitter.
FIG. 1B
illustrates how accumulative jitter samples, T
J(I)
for I=1, . . . , N can be collected using a TDC.
Sometimes, the relative jitter between two signals is of interest if neither of the two signals is a jitter-free signal, e.g. in data recovery circuits. FIG.
1
C shows how relative jitter between the edges of signal IN
1
and IN
2
can be measured using a TDC.
Intrinsic jitter is defined as the jitter at the output of the PLL when the input is jitter-free. This is often expressed in terms of unit interval UI, which is defined as the period of a signal with a frequency equal to the average frequency of the original signal. For example in a 155.54 MHz SONET network application, 1 UI is 6.429 ns.
Functional testing is typically used to test today's high-speed timing circuits. Functional testing, however, does not guarantee correct operation over all operational conditions. Structural test methods are proposed as test solutions, but most of them are too intrusive (i.e. the testing itself has a significant effect on the performance of the circuit) or provide poor correlation to important specifications such as jitter. Jitter specifications are typically the single most important set of specifications for a high-speed timing circuit. Jitter specifications include intrinsic jitter, jitter transfer functions and jitter tolerance. Testing such a circuit to determine whether its actual jitter characteristics meet its specifications is a significant problem.
There is a need for systems capable of measuring jitter characteristics of high-speed digital signals. There is a particular need for such systems capable of measuring jitter in timing circuits internal to complicated integrated circuits.
Various authors have proposed methods for testing devices such as PLLs. All of these proposed methods have disadvantages. R. J. A. Harvey et al.
Test evaluation for complex mixed
-
signal IC's by introducing layout dependent faults
, IEEE Colloquium on Mixed Signal VLSI Test, pp. 6/1-8, 1993 suggests testing PLLs by performing partial specification testing by measuring lock range, lock time and power supply current. Dalmia et al.
Power supply current monitoring techniques for testing PLLs
Proc. of Asian Test Symposium, pp. 366-371, 1997 and Dalmia et al., U.S. Pat. No. 5,835,501 disclose the use of power supply current monitoring for PLL testing.
Devarayanadurg et al.
Hierarchy based statistical fault simulation of mixed signal IC's
Int. Test Conf. pp. 521-527, 1996 and Goteti et al.
DFT for embedded charge
-
pump PLL systems incorporating IEEE
1149.1, Proc. of Custom Integrated Circuits Conf. pp. 210-213, 1997 propose methods for efficient fault simulation of PLLs and suggest lock frequency range measurement for PLL testing.
Although a combination of these techniques may provide an effective test result, it is difficult to correlate the test results to important jitter specifications. This is partly because simulating jitter for fault-free and faulty circuits is extremely difficult due to a lack of tools capable of simulating noise in non-linear dynamic circuits.
Azias et al.
A unified digital test technique for PLLs using reconfigurable VCO
Proc. of Int. Mixed Signal Test Workshop, 1999 discloses a reconfiguration technique for testing ring oscillator-based PLLS. This technique has the advantage of being compatible with digital test methods, but it requires reconfiguring sensitive parts of a PLL. Also, it exhibits the problem of unknown correlation of test results and functional specifications.
S. Sunter et al.
BIST for phase
-
locked loops in digital applications
, Proc. of Int. Test Conf. pp. 532-540, 1999 discloses a BIST circuit capable of measuring lock range and loop gain of a PLL in addition to performing a jitter test. Methods which use this circuit to measure jitter depend on bit error rate (BER) and so can only provide statistical information about jitter. Such methods may give pessimistic estimates of jitter in noisy digital environments. This might lead to discarding some good devices.
U.S. Pat. Nos. 5,663,991 and 5,889,435 disclose on-chip
Ivanov Andre
Tabatabaei Sassan
Barlow John
Lau Tung
Oyen Wiggs Green & Mutala
Vector 12 Corporation
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