High resolution time-to-digital converter

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C327S001000, C331S00100A

Reexamination Certificate

active

07978111

ABSTRACT:
A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.

REFERENCES:
patent: 6801150 (2004-10-01), Honda
patent: 2006/0103566 (2006-05-01), Vemulapalli et al.
Christiansen: “An integrated high resolution CMOS timing generator based on an array of delay locked loops,” IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US, vol. 31, No. 7, Jul. 1996, pp. 952-957, ISSN: 0018-9200.
International Search Report and Written Opinion—PCT/US2009/035913—International Search Authority, EPO—May 29, 2009.
Mota, et al: “A four-channel self-calibrating high-resolution time to digital converter,” Electronica, Circuits, and Systems, 1998, IEEE Intl Conference on, Lisboa, Portugal, Sep. 7-10, 1998, IEEE Piscataway, NJ, US, pp. 409-412, ISBN: 978-07803-5008-3.

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